reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
8868 case MCK_CondCodeRestrictedI: { 9722 case MCK_CondCodeRestrictedI: return "MCK_CondCodeRestrictedI"; 12130 { 2158 /* vcmp */, ARM::MVE_VCMPi16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12131 { 2158 /* vcmp */, ARM::MVE_VCMPi16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12132 { 2158 /* vcmp */, ARM::MVE_VCMPi32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12133 { 2158 /* vcmp */, ARM::MVE_VCMPi32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12134 { 2158 /* vcmp */, ARM::MVE_VCMPi8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 12135 { 2158 /* vcmp */, ARM::MVE_VCMPi8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13658 { 2963 /* vpt */, ARM::MVE_VPTv8i16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 13659 { 2963 /* vpt */, ARM::MVE_VPTv8i16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13660 { 2963 /* vpt */, ARM::MVE_VPTv4i32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 13661 { 2963 /* vpt */, ARM::MVE_VPTv4i32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13662 { 2963 /* vpt */, ARM::MVE_VPTv16i8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, }, 13663 { 2963 /* vpt */, ARM::MVE_VPTv16i8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 15686 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15687 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15688 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15689 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15690 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15691 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15987 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15988 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15989 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15990 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15991 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 15992 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt }, 16327 case MCK_CondCodeRestrictedI: