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References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
 7364   case MCK_AM3Offset: {
 9522   case MCK_AM3Offset: return "MCK_AM3Offset";
10657   { 559 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10680   { 591 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10698   { 602 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10716   { 615 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11319   { 1552 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11339   { 1584 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
15471   { 559 /* ldrd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM },
15472   { 591 /* ldrh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
15474   { 602 /* ldrsb */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
15476   { 615 /* ldrsh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
15630   { 1552 /* strd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM },
15631   { 1584 /* strh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
16211   case MCK_AM3Offset: