reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc

12195   { 2185 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12197   { 2185 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12200   { 2185 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12202   { 2185 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12209   { 2185 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12211   { 2185 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12214   { 2185 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12216   { 2185 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12222   { 2185 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12224   { 2185 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12228   { 2185 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12230   { 2185 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12237   { 2185 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12239   { 2185 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12243   { 2185 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12245   { 2185 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },