reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
13918 { 3239 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13920 { 3239 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13922 { 3248 /* vqrshrnt */, ARM::MVE_VQRSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13924 { 3248 /* vqrshrnt */, ARM::MVE_VQRSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13929 { 3266 /* vqrshrunb */, ARM::MVE_VQRSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 13931 { 3276 /* vqrshrunt */, ARM::MVE_VQRSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14040 { 3306 /* vqshrnb */, ARM::MVE_VQSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14042 { 3306 /* vqshrnb */, ARM::MVE_VQSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14044 { 3314 /* vqshrnt */, ARM::MVE_VQSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14046 { 3314 /* vqshrnt */, ARM::MVE_VQSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14051 { 3330 /* vqshrunb */, ARM::MVE_VQSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14053 { 3339 /* vqshrunt */, ARM::MVE_VQSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14367 { 3594 /* vrshrnb */, ARM::MVE_VRSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14369 { 3602 /* vrshrnt */, ARM::MVE_VRSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14570 { 3735 /* vshrnb */, ARM::MVE_VSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14572 { 3742 /* vshrnt */, ARM::MVE_VSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, }, 14645 { 3765 /* vsri */, ARM::MVE_VSRIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },