reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc

13127   { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13128   { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13129   { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13130   { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13137   { 2648 /* vmlaldavx */, ARM::MVE_VMLALDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13138   { 2648 /* vmlaldavx */, ARM::MVE_VMLALDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13139   { 2658 /* vmlalv */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13140   { 2658 /* vmlalv */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13141   { 2658 /* vmlalv */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13142   { 2658 /* vmlalv */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13208   { 2739 /* vmlsldav */, ARM::MVE_VMLSLDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13209   { 2739 /* vmlsldav */, ARM::MVE_VMLSLDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13214   { 2769 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13215   { 2769 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14261   { 3453 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14262   { 3453 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14266   { 3489 /* vrmlaldavhx */, ARM::MVE_VRMLALDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14267   { 3501 /* vrmlalvh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14268   { 3501 /* vrmlalvh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14271   { 3520 /* vrmlsldavh */, ARM::MVE_VRMLSLDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14274   { 3556 /* vrmlsldavhx */, ARM::MVE_VRMLSLDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },