reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc

10583   { 522 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10584   { 522 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10587   { 522 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10589   { 526 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10591   { 526 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10595   { 532 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10596   { 532 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10599   { 532 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10601   { 538 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10603   { 538 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11257   { 1515 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
11258   { 1515 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11259   { 1515 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11262   { 1515 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11264   { 1519 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11266   { 1519 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11270   { 1525 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11271   { 1525 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11274   { 1525 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11276   { 1531 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11278   { 1531 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },