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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10555 { 506 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10559 { 506 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10560 { 506 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10561 { 506 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10563 { 511 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10567 { 511 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10568 { 511 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10569 { 511 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11216 { 1458 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11220 { 1458 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11221 { 1458 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11222 { 1458 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11224 { 1463 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11228 { 1463 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11229 { 1463 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11230 { 1463 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
15416 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15417 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15425 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15426 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15427 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15428 { 506 /* ldc2 */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15429 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15430 { 506 /* ldc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15431 { 506 /* ldc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15434 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15435 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15443 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15444 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15445 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15446 { 511 /* ldc2l */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15447 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15448 { 511 /* ldc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15449 { 511 /* ldc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15575 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15576 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15584 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15585 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15586 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15587 { 1458 /* stc2 */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15588 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15589 { 1458 /* stc2 */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15590 { 1458 /* stc2 */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15593 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15594 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15602 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15603 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15604 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15605 { 1463 /* stc2l */, 16 /* 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15606 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15607 { 1463 /* stc2l */, 2 /* 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15608 { 1463 /* stc2l */, 4 /* 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },