reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
10325 { 63 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, }, 10382 { 130 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 10383 { 135 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 10658 { 564 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 10660 { 570 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10664 { 584 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 10781 { 687 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, }, 10811 { 696 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 10813 { 701 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 11320 { 1557 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 11322 { 1563 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 11326 { 1577 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },