|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10379 { 121 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, },
10423 { 186 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm0_31 }, },
10428 { 186 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, },
10430 { 186 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, },
10663 { 577 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
10833 { 726 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, },
10835 { 726 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, },
10838 { 730 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
10976 { 883 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
10977 { 883 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
10980 { 889 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
10981 { 889 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
11176 { 1388 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11178 { 1388 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11186 { 1407 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11188 { 1407 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11325 { 1570 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11380 { 1604 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_GPRlr, MCK_Imm0_255 }, },
15374 { 186 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
15376 { 186 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
15533 { 730 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsThumb2_IsNotMClass },