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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10204 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10205 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10206 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10208 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10213 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
10214 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10215 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10217 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10234 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10235 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10237 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10238 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10255 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10256 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10258 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10259 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10271 { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, },
10282 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10283 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10285 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10286 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10295 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10296 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10298 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10299 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10308 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10309 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
10315 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10316 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
10321 { 63 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10340 { 96 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10341 { 96 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10343 { 96 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10344 { 96 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10353 { 96 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10354 { 96 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10356 { 96 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10357 { 96 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10362 { 100 /* bkpt */, ARM::BKPT, Convert__imm_95_0, AMFBS_IsARM, { }, },
10365 { 100 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
10366 { 105 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, AMFBS_IsARM, { MCK_ARMBranchTarget }, },
10367 { 105 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10380 { 121 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR }, },
10400 { 173 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10402 { 173 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10403 { 173 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10404 { 173 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10413 { 177 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10415 { 177 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10417 { 177 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10418 { 177 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10424 { 186 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
10426 { 186 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags }, },
10429 { 186 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, },
10477 { 318 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10478 { 318 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10479 { 318 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10480 { 318 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10487 { 318 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10488 { 318 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10489 { 318 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10490 { 318 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10529 { 453 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsARM, { MCK_ITMask, MCK_ITCondCode }, },
10546 { 502 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10548 { 502 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10550 { 502 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10552 { 502 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10570 { 517 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10572 { 517 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10574 { 517 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10576 { 517 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10579 { 522 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10583 { 522 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10585 { 522 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10587 { 522 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10588 { 526 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10589 { 526 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10590 { 526 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10591 { 526 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10592 { 532 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10595 { 532 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10597 { 532 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10599 { 532 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10600 { 538 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10601 { 538 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10602 { 538 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10603 { 538 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10610 { 544 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
10612 { 544 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
10613 { 544 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
10623 { 544 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10625 { 544 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10627 { 544 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10628 { 544 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10634 { 548 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
10636 { 548 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
10642 { 548 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10644 { 548 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10646 { 548 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10647 { 548 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10649 { 553 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10650 { 553 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10651 { 553 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10656 { 559 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10657 { 559 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10659 { 564 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10661 { 570 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10662 { 577 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
10665 { 584 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10673 { 591 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10678 { 591 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10680 { 591 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10683 { 596 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10684 { 596 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10691 { 602 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10696 { 602 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10698 { 602 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10701 { 608 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10702 { 608 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10709 { 615 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10714 { 615 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10716 { 615 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10719 { 621 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10720 { 621 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10722 { 628 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10723 { 628 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10724 { 628 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10732 { 641 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10733 { 641 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
10740 { 641 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10741 { 641 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
10751 { 650 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10752 { 650 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
10758 { 650 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10759 { 650 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
10763 { 659 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
10765 { 659 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10767 { 663 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
10771 { 668 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
10777 { 679 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10780 { 687 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_PC, MCK_GPRlr }, },
10788 { 687 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, },
10791 { 687 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10792 { 687 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10793 { 687 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10794 { 687 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10815 { 706 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
10817 { 706 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10819 { 710 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
10823 { 715 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
10829 { 726 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, },
10830 { 726 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, },
10831 { 726 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, },
10840 { 730 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, },
10841 { 730 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, },
10848 { 734 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10855 { 738 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10856 { 738 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10857 { 738 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10858 { 738 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10864 { 742 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10868 { 746 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, AMFBS_IsARM, { MCK_CondCode }, },
10883 { 754 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10884 { 754 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10885 { 754 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10886 { 754 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10894 { 754 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10895 { 754 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10896 { 754 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10897 { 754 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10909 { 770 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, AMFBS_IsARM, { MCK_MemImm12Offset }, },
10910 { 770 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, AMFBS_IsARM, { MCK_MemRegOffset }, },
10930 { 783 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
10936 { 793 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
10939 { 798 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10941 { 803 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10943 { 810 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10945 { 816 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10947 { 821 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10949 { 827 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10951 { 833 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10953 { 838 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10955 { 843 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10957 { 850 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10972 { 877 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
10973 { 877 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
10974 { 883 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
10975 { 883 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
10978 { 889 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
10979 { 889 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
10982 { 895 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
10983 { 895 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
10987 { 901 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10988 { 901 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
10993 { 901 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10994 { 901 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
10998 { 905 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11002 { 909 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11003 { 909 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11004 { 909 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11005 { 909 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11010 { 909 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11011 { 909 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11012 { 909 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11013 { 909 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11015 { 913 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11016 { 913 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11017 { 913 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11018 { 913 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11019 { 913 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11020 { 913 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11021 { 913 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11022 { 913 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11024 { 917 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11026 { 924 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11028 { 930 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11032 { 938 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11033 { 938 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11034 { 938 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11036 { 938 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11041 { 938 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
11042 { 938 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11043 { 938 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11045 { 938 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11055 { 956 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, AMFBS_IsARM, { MCK_SetEndImm }, },
11076 { 1059 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11078 { 1067 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11080 { 1074 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11082 { 1080 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11084 { 1086 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11086 { 1094 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11099 { 1132 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11150 { 1307 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11167 { 1382 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11168 { 1382 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11169 { 1382 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11170 { 1382 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11171 { 1388 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11172 { 1388 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11174 { 1388 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11175 { 1388 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11181 { 1407 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11182 { 1407 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11184 { 1407 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11185 { 1407 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11189 { 1413 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11190 { 1413 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11191 { 1413 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11192 { 1413 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11194 { 1419 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, },
11200 { 1431 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11204 { 1441 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11206 { 1448 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11207 { 1454 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11209 { 1454 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11211 { 1454 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11213 { 1454 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11231 { 1469 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11233 { 1469 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11235 { 1469 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11237 { 1469 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11253 { 1515 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11258 { 1515 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11260 { 1515 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11262 { 1515 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11263 { 1519 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11264 { 1519 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11265 { 1519 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11266 { 1519 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11267 { 1525 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11270 { 1525 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11272 { 1525 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11274 { 1525 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11275 { 1531 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11276 { 1531 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11277 { 1531 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11278 { 1531 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11282 { 1537 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
11284 { 1537 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
11291 { 1537 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11292 { 1537 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11293 { 1537 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11294 { 1537 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11300 { 1541 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
11301 { 1541 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
11306 { 1541 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11307 { 1541 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11308 { 1541 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11309 { 1541 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11311 { 1546 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11312 { 1546 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11313 { 1546 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11318 { 1552 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11319 { 1552 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11321 { 1557 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11323 { 1563 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11324 { 1570 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
11327 { 1577 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11333 { 1584 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
11338 { 1584 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11339 { 1584 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11341 { 1589 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
11342 { 1589 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, },
11344 { 1595 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11345 { 1595 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11346 { 1595 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11355 { 1600 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11356 { 1600 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11358 { 1600 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11359 { 1600 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11371 { 1600 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11372 { 1600 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11374 { 1600 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11375 { 1600 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11385 { 1614 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_Imm24bit }, },
11389 { 1627 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11393 { 1633 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11397 { 1641 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11402 { 1647 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11408 { 1652 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11414 { 1659 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11424 { 1672 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11425 { 1672 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11426 { 1672 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11427 { 1672 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11432 { 1676 /* trap */, ARM::TRAP, Convert_NoOperands, AMFBS_IsARM, { }, },
11440 { 1685 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11441 { 1685 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11442 { 1685 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11443 { 1685 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11452 { 1705 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11454 { 1712 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11456 { 1718 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11460 { 1728 /* udf */, ARM::UDF, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
11465 { 1737 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11467 { 1745 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11469 { 1752 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11471 { 1758 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11473 { 1764 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11475 { 1772 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11480 { 1785 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11483 { 1791 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11485 { 1797 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11487 { 1805 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11489 { 1812 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11493 { 1833 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11497 { 1852 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11499 { 1860 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11507 { 1893 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, },
11513 { 1905 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11515 { 1910 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11517 { 1917 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11519 { 1923 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11523 { 1929 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11527 { 1937 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11532 { 1943 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11538 { 1948 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11544 { 1955 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
15346 { 10 /* adc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15347 { 10 /* adc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15348 { 14 /* add */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15349 { 14 /* add */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15350 { 50 /* and */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15351 { 50 /* and */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15357 { 96 /* bic */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15358 { 96 /* bic */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15369 { 173 /* cmn */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM },
15370 { 177 /* cmp */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM },
15372 { 186 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
15375 { 186 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
15388 { 318 /* eor */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15389 { 318 /* eor */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15394 { 453 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsARM },
15396 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15397 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15400 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15401 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15404 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15405 { 502 /* ldc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM },
15406 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15410 { 502 /* ldc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15411 { 502 /* ldc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15450 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15451 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15454 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15455 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15458 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15459 { 517 /* ldcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM },
15460 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15464 { 517 /* ldcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15465 { 517 /* ldcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15468 { 544 /* ldr */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15469 { 548 /* ldrb */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15470 { 553 /* ldrbt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15471 { 559 /* ldrd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM },
15472 { 591 /* ldrh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
15473 { 596 /* ldrht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15474 { 602 /* ldrsb */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
15475 { 608 /* ldrsbt */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15476 { 615 /* ldrsh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
15477 { 621 /* ldrsht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15478 { 628 /* ldrt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15479 { 659 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15480 { 659 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15483 { 659 /* mcr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15484 { 659 /* mcr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15487 { 663 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
15488 { 663 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
15495 { 668 /* mcrr */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15496 { 668 /* mcrr */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsARM },
15503 { 687 /* mov */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15504 { 706 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15505 { 706 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15508 { 706 /* mrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15509 { 706 /* mrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15512 { 710 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
15513 { 710 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
15520 { 715 /* mrrc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15521 { 715 /* mrrc */, 32 /* 5 */, MCK_CoprocReg, AMFBS_IsARM },
15535 { 730 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsARM },
15536 { 730 /* msr */, 2 /* 1 */, MCK_MSRMask, AMFBS_IsARM },
15537 { 730 /* msr */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM },
15538 { 738 /* mvn */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15539 { 754 /* orr */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15540 { 754 /* orr */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15545 { 909 /* rsb */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15546 { 909 /* rsb */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15547 { 913 /* rsc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15548 { 913 /* rsc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15549 { 938 /* sbc */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15550 { 938 /* sbc */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15552 { 956 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsARM },
15555 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15556 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15559 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15560 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15563 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15564 { 1454 /* stc */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM },
15565 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15569 { 1454 /* stc */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15570 { 1454 /* stc */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15609 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15610 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15613 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15614 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15617 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15618 { 1469 /* stcl */, 16 /* 4 */, MCK_CoprocOption, AMFBS_IsARM },
15619 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15623 { 1469 /* stcl */, 2 /* 1 */, MCK_CoprocNum, AMFBS_IsARM },
15624 { 1469 /* stcl */, 4 /* 2 */, MCK_CoprocReg, AMFBS_IsARM },
15627 { 1537 /* str */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15628 { 1541 /* strb */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15629 { 1546 /* strbt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15630 { 1552 /* strd */, 16 /* 4 */, MCK_AM3Offset, AMFBS_IsARM },
15631 { 1584 /* strh */, 8 /* 3 */, MCK_AM3Offset, AMFBS_IsARM },
15632 { 1589 /* strht */, 8 /* 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15633 { 1595 /* strt */, 8 /* 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15634 { 1600 /* sub */, 8 /* 3 */, MCK_ModImm, AMFBS_IsARM },
15635 { 1600 /* sub */, 16 /* 4 */, MCK_ModImm, AMFBS_IsARM },
15651 { 1672 /* teq */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM },
15654 { 1685 /* tst */, 4 /* 2 */, MCK_ModImm, AMFBS_IsARM },