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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARC/ARCGenInstrInfo.inc 621 static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
621 static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
622 static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
623 static const MCOperandInfo OperandInfo38[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
624 static const MCOperandInfo OperandInfo39[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
624 static const MCOperandInfo OperandInfo39[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
626 static const MCOperandInfo OperandInfo41[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
627 static const MCOperandInfo OperandInfo42[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
627 static const MCOperandInfo OperandInfo42[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
628 static const MCOperandInfo OperandInfo43[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
628 static const MCOperandInfo OperandInfo43[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
628 static const MCOperandInfo OperandInfo43[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
629 static const MCOperandInfo OperandInfo44[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
629 static const MCOperandInfo OperandInfo44[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
630 static const MCOperandInfo OperandInfo45[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
631 static const MCOperandInfo OperandInfo46[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
631 static const MCOperandInfo OperandInfo46[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
632 static const MCOperandInfo OperandInfo47[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
632 static const MCOperandInfo OperandInfo47[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
634 static const MCOperandInfo OperandInfo49[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
635 static const MCOperandInfo OperandInfo50[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
637 static const MCOperandInfo OperandInfo52[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
638 static const MCOperandInfo OperandInfo53[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
638 static const MCOperandInfo OperandInfo53[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
638 static const MCOperandInfo OperandInfo53[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
639 static const MCOperandInfo OperandInfo54[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
639 static const MCOperandInfo OperandInfo54[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
639 static const MCOperandInfo OperandInfo54[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
640 static const MCOperandInfo OperandInfo55[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
640 static const MCOperandInfo OperandInfo55[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
640 static const MCOperandInfo OperandInfo55[] = { { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARC::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 265 { GPR32, GPR32Bits, 0, 32, sizeof(GPR32Bits), ARC::GPR32RegClassID, 1, true },
630 &ARCMCRegisterClasses[GPR32RegClassID],