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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 1081 /* 3489*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
1150 /* 3793*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
1219 /* 4097*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
1288 /* 4401*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
1363 /* 4715*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
1428 /* 5003*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
1505 /* 5319*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
1570 /* 5607*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
2382 /* 9123*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
2494 /* 9631*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
2611 /* 10148*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
2724 /* 10657*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
2841 /* 11174*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
2953 /* 11682*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
3070 /* 12199*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
3183 /* 12708*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
3305 /* 13232*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
3416 /* 13739*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
3625 /* 14718*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
3748 /* 15243*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
3859 /* 15750*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
4068 /* 16729*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6187 /* 24179*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6253 /* 24468*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6324 /* 24766*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6391 /* 25056*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6467 /* 25363*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6529 /* 25647*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6601 /* 25946*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
6663 /* 26230*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
10730 /* 41010*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
10795 /* 41298*/ OPC_EmitInteger, MVT::i32, R600::R600_Reg64RegClassID,
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 626 static const MCOperandInfo OperandInfo67[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
630 static const MCOperandInfo OperandInfo71[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
635 static const MCOperandInfo OperandInfo76[] = { { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 7068 { R600_Reg64, R600_Reg64Bits, 62, 64, sizeof(R600_Reg64Bits), R600::R600_Reg64RegClassID, 1, true },
9565 &R600MCRegisterClasses[R600_Reg64RegClassID],
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2787 case 2: RegClassID = R600::R600_Reg64RegClassID; break;