reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/R600GenInstrInfo.inc
  877   { 239,	14,	1,	0,	2,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #239 = BCNT_INT
  883   { 245,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #245 = CEIL
  916   { 278,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #278 = COS_cm
  917   { 279,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #279 = COS_eg
  918   { 280,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #280 = COS_r600
  919   { 281,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #281 = COS_r700
  928   { 290,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #290 = EXP_IEEE_cm
  929   { 291,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #291 = EXP_IEEE_eg
  930   { 292,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #292 = EXP_IEEE_r600
  932   { 294,	14,	1,	0,	2,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #294 = FFBH_UINT
  933   { 295,	14,	1,	0,	2,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #295 = FFBL_INT
  934   { 296,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #296 = FLOOR
  935   { 297,	14,	1,	0,	2,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #297 = FLT16_TO_FLT32
  936   { 298,	14,	1,	0,	2,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #298 = FLT32_TO_FLT16
  937   { 299,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #299 = FLT_TO_INT_eg
  938   { 300,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #300 = FLT_TO_INT_r600
  939   { 301,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #301 = FLT_TO_UINT_eg
  940   { 302,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #302 = FLT_TO_UINT_r600
  942   { 304,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #304 = FRACT
  944   { 306,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #306 = INTERP_LOAD_P0
  950   { 312,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #312 = INT_TO_FLT_eg
  951   { 313,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #313 = INT_TO_FLT_r600
  984   { 346,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #346 = LOG_CLAMPED_eg
  985   { 347,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #347 = LOG_CLAMPED_r600
  986   { 348,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #348 = LOG_IEEE_cm
  987   { 349,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #349 = LOG_IEEE_eg
  988   { 350,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #350 = LOG_IEEE_r600
 1003   { 365,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #365 = MOV
 1004   { 366,	14,	1,	0,	2,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #366 = MOVA_INT_eg
 1032   { 394,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #394 = NOT_INT
 1084   { 446,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #446 = RECIPSQRT_CLAMPED_cm
 1085   { 447,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #447 = RECIPSQRT_CLAMPED_eg
 1086   { 448,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #448 = RECIPSQRT_CLAMPED_r600
 1087   { 449,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #449 = RECIPSQRT_IEEE_cm
 1088   { 450,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #450 = RECIPSQRT_IEEE_eg
 1089   { 451,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #451 = RECIPSQRT_IEEE_r600
 1090   { 452,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #452 = RECIP_CLAMPED_cm
 1091   { 453,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #453 = RECIP_CLAMPED_eg
 1092   { 454,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #454 = RECIP_CLAMPED_r600
 1093   { 455,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4640ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #455 = RECIP_IEEE_cm
 1094   { 456,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #456 = RECIP_IEEE_eg
 1095   { 457,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #457 = RECIP_IEEE_r600
 1096   { 458,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #458 = RECIP_UINT_eg
 1097   { 459,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #459 = RECIP_UINT_r600
 1098   { 460,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #460 = RNDNE
 1112   { 474,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4650ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #474 = SIN_cm
 1113   { 475,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #475 = SIN_eg
 1114   { 476,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #476 = SIN_r600
 1115   { 477,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4610ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #477 = SIN_r700
 1136   { 498,	14,	1,	0,	3,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #498 = TRUNC
 1137   { 499,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #499 = UINT_TO_FLT_eg
 1138   { 500,	14,	1,	0,	4,	0|(1ULL<<MCID::Predicable), 0x4600ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #500 = UINT_TO_FLT_r600