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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15630 static const MCOperandInfo OperandInfo288[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15630 static const MCOperandInfo OperandInfo288[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15638 static const MCOperandInfo OperandInfo296[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15639 static const MCOperandInfo OperandInfo297[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
15650 static const MCOperandInfo OperandInfo308[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
15651 static const MCOperandInfo OperandInfo309[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15657 static const MCOperandInfo OperandInfo315[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15658 static const MCOperandInfo OperandInfo316[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15658 static const MCOperandInfo OperandInfo316[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15659 static const MCOperandInfo OperandInfo317[] = { { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15659 static const MCOperandInfo OperandInfo317[] = { { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15667 static const MCOperandInfo OperandInfo325[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15668 static const MCOperandInfo OperandInfo326[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
15669 static const MCOperandInfo OperandInfo327[] = { { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
15682 static const MCOperandInfo OperandInfo340[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15683 static const MCOperandInfo OperandInfo341[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15683 static const MCOperandInfo OperandInfo341[] = { { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15684 static const MCOperandInfo OperandInfo342[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15684 static const MCOperandInfo OperandInfo342[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15686 static const MCOperandInfo OperandInfo344[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15686 static const MCOperandInfo OperandInfo344[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15691 static const MCOperandInfo OperandInfo349[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
15692 static const MCOperandInfo OperandInfo350[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15705 static const MCOperandInfo OperandInfo363[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15705 static const MCOperandInfo OperandInfo363[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15705 static const MCOperandInfo OperandInfo363[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15707 static const MCOperandInfo OperandInfo365[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
15707 static const MCOperandInfo OperandInfo365[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
15707 static const MCOperandInfo OperandInfo365[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
15738 static const MCOperandInfo OperandInfo396[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15743 static const MCOperandInfo OperandInfo401[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15760 static const MCOperandInfo OperandInfo418[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
15761 static const MCOperandInfo OperandInfo419[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15761 static const MCOperandInfo OperandInfo419[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15762 static const MCOperandInfo OperandInfo420[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15772 static const MCOperandInfo OperandInfo430[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 77 (1u << (AMDGPU::VS_64RegClassID - 0)) |
198 (1u << (AMDGPU::VS_64RegClassID - 0)) |
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11268 { VS_64, VS_64Bits, 3007, 322, sizeof(VS_64Bits), AMDGPU::VS_64RegClassID, 1, false },
20636 &AMDGPUMCRegisterClasses[VS_64RegClassID],
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 259 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);
271 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);
453 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);
469 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1092 case AMDGPU::VS_64RegClassID: