reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

17349   extern const TargetRegisterClass VReg_64RegClass;

References

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

21734     &AMDGPU::VReg_64RegClass,

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

  785         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  344     = IsSALU ? AMDGPU::SReg_64_XEXECRegClass : AMDGPU::VReg_64RegClass;

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

  839               MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass);

lib/Target/AMDGPU/SIISelLowering.cpp

  123   addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
  125   addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
10586         RC = &AMDGPU::VReg_64RegClass;

lib/Target/AMDGPU/SIInstrInfo.cpp

  779   if (RegClass == &AMDGPU::VReg_64RegClass) {
 3841   if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
 3842     VRC = &AMDGPU::VReg_64RegClass;
 4480                              AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
 4700       Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
 4744       Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
 5349   Register FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
 5576     Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
 5600   Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

  902       (CI.EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass;
 1286       return &AMDGPU::VReg_64RegClass;
 1415   Register FullDestReg = MRI->createVirtualRegister(&AMDGPU::VReg_64RegClass);

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1251     &AMDGPU::VReg_64RegClass,
 1290     return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr;
 1342     return &AMDGPU::VReg_64RegClass;
 1450       return &AMDGPU::VReg_64RegClass;
 1805     return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  236     RC = &AMDGPU::VReg_64RegClass;