reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

17329   extern const TargetRegisterClass VReg_1RegClass;

References

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

21714     &AMDGPU::VReg_1RegClass,

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  190   return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) &&
  197   return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) &&
  788           UseRC != &AMDGPU::VReg_1RegClass)
  832        RC0 != &AMDGPU::VReg_1RegClass) &&

lib/Target/AMDGPU/SIISelLowering.cpp

  117   addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
10260         MRI.createVirtualRegister(&AMDGPU::VReg_1RegClass), MVT::i1);
10940   if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)

lib/Target/AMDGPU/SIInstrInfo.cpp

 4300   if (Def->isMoveImmediate() && DstRC != &AMDGPU::VReg_1RegClass)
 4560         if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) {
 4561           VRC = &AMDGPU::VReg_1RegClass;
 5767       if (RI.hasVGPRs(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass)

lib/Target/AMDGPU/SILowerI1Copies.cpp

  100            MRI->getRegClass(Reg) == &AMDGPU::VReg_1RegClass;

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1304     return getCommonSubClass(&AMDGPU::VReg_1RegClass, RC) != nullptr;
 1356     return &AMDGPU::VReg_1RegClass;