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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17334 extern const TargetRegisterClass VGPR_32RegClass;
References
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc21719 &AMDGPU::VGPR_32RegClass,
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp 126 &AMDGPU::VGPR_32RegClass);
129 &AMDGPU::VGPR_32RegClass);
132 &AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 654 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
773 } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 346 = IsSALU ? AMDGPU::SReg_32RegClass : AMDGPU::VGPR_32RegClass;
954 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
959 Register OverflowVal = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
964 Register NewBaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1058 Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1443 &AMDGPU::SReg_32RegClass : &AMDGPU::VGPR_32RegClass;
1609 DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI);
1627 = IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass;
2009 Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 780 constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI);
871 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass);
1013 constrainGenericRegister(Reg, AMDGPU::VGPR_32RegClass, MRI);
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp 1142 AMDGPU::VGPR_32RegClass,
1145 AMDGPU::VGPR_32RegClass,
1148 AMDGPU::VGPR_32RegClass,
lib/Target/AMDGPU/GCNDPPCombine.cpp 179 assert(isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI));
330 if (!isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI)) {
436 MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));
lib/Target/AMDGPU/GCNNSAReassign.cpp 194 if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())
lib/Target/AMDGPU/GCNRegBankReassign.cpp 329 unsigned StartBit = AMDGPU::VGPR_32RegClass.getNumRegs();
748 RegsUsed.resize(AMDGPU::VGPR_32RegClass.getNumRegs() +
lib/Target/AMDGPU/GCNSchedStrategy.cpp 46 ->getNumAllocatableRegs(&AMDGPU::VGPR_32RegClass) - ErrorMargin;
lib/Target/AMDGPU/SIAddIMGInit.cpp 154 MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIFoldOperands.cpp 745 Vgpr = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 320 MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count();
lib/Target/AMDGPU/SIFrameLowering.cpp 121 MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass);
168 MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIISelLowering.cpp 121 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
1622 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1630 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1638 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1655 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1669 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
3436 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3437 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3759 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3760 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5844 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5849 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5854 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
10583 RC = &AMDGPU::VGPR_32RegClass;
10640 RC = &AMDGPU::VGPR_32RegClass;
lib/Target/AMDGPU/SIInstrInfo.cpp 530 if (RC == &AMDGPU::VGPR_32RegClass) {
531 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
556 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
582 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
610 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
613 if (!AMDGPU::VGPR_32RegClass.contains(SrcReg)) {
650 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
656 unsigned Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
663 while (RegNo-- && RS.FindUnusedReg(&AMDGPU::VGPR_32RegClass)) {
664 unsigned Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
774 if (RegClass == &AMDGPU::VGPR_32RegClass) {
809 return &AMDGPU::VGPR_32RegClass;
823 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
1098 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1217 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1244 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
1582 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2210 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
3844 VRC = &AMDGPU::VGPR_32RegClass;
4698 Register NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4699 Register NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5112 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5145 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5146 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5175 Register NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5176 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
5177 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src1, MRI, DL);
5350 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5351 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5534 Register MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5535 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5574 Register MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5575 Register MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5599 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5655 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5663 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5664 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5682 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5692 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5693 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 915 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1008 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1394 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1395 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 290 LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
344 isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1192 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIRegisterInfo.cpp 200 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
202 unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
364 Register FIReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
429 return &AMDGPU::VGPR_32RegClass;
821 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
917 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1108 RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1123 RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MIB, 0);
1229 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1248 &AMDGPU::VGPR_32RegClass,
1288 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
1340 return &AMDGPU::VGPR_32RegClass;
1448 return &AMDGPU::VGPR_32RegClass;
1752 return getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
1783 return &AMDGPU::VGPR_32RegClass;
1802 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
1827 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :