reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

17350   extern const TargetRegisterClass SReg_64RegClass;

References

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

19767   &AMDGPU::SReg_64RegClass,
19778   &AMDGPU::SReg_64RegClass,
19790   &AMDGPU::SReg_64RegClass,
19803   &AMDGPU::SReg_64RegClass,
21735     &AMDGPU::SReg_64RegClass,

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

  780         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  273                                            RC == &AMDGPU::SReg_64RegClass);
 1241         DstSize > 32 ? &AMDGPU::SReg_64RegClass : &AMDGPU::SReg_32RegClass;
 1320       Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
 1334       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI);

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 1627   B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 1104                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
 1106        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
 1109                              AMDGPU::SReg_64RegClass,
 1112                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
 1115                              AMDGPU::SReg_64RegClass,
 1136                              AMDGPU::SReg_64RegClass,
 1139                              AMDGPU::SReg_64RegClass,

lib/Target/AMDGPU/SIISelLowering.cpp

  118   addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
  124   addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
  152     addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
  153     addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
 1996     if (AMDGPU::SReg_64RegClass.contains(*I))
 2296       DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
 2347         if (AMDGPU::SReg_64RegClass.contains(*I))
 2899       DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
 4615     DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
 4679     DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
10941     return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass

lib/Target/AMDGPU/SIInstrInfo.cpp

  575   if (RC == &AMDGPU::SReg_64RegClass) {
  577       if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
  591     if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
  766   if (RegClass == &AMDGPU::SReg_64RegClass ||
 1782   Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
 1854     AMDGPU::SReg_64RegClass,
 3128            AMDGPU::SReg_64RegClass.contains(MO.getReg());
 4483   Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
 5491   Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);

lib/Target/AMDGPU/SILowerI1Copies.cpp

  431                                                  : &AMDGPU::SReg_64RegClass);
  571                                       : &AMDGPU::SReg_64RegClass);
  692                                         : &AMDGPU::SReg_64RegClass);

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

  199     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
  206     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
  214     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
  221     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
  228     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
  235     getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1252     &AMDGPU::SReg_64RegClass,
 1386     return &AMDGPU::SReg_64RegClass;
 1416       return &AMDGPU::SReg_64RegClass;

lib/Target/AMDGPU/SIRegisterInfo.h

  267                     : &AMDGPU::SReg_64RegClass;