reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

17338   extern const TargetRegisterClass SReg_32_XM0RegClass;

References

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

19686   &AMDGPU::SReg_32_XM0RegClass,
19697   &AMDGPU::SReg_32_XM0RegClass,
19709   &AMDGPU::SReg_32_XM0RegClass,
19722   &AMDGPU::SReg_32_XM0RegClass,
21723     &AMDGPU::SReg_32_XM0RegClass,

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

  777             = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
  840               MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass);
  841               MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass);
  872               MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass);
 1007   Register SGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  623               = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);

lib/Target/AMDGPU/SIFrameLowering.cpp

  787         MRI, LiveRegs, AMDGPU::SReg_32_XM0RegClass);

lib/Target/AMDGPU/SIISelLowering.cpp

 3143   Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 3361       Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);

lib/Target/AMDGPU/SIInstrInfo.cpp

  541   if (RC == &AMDGPU::SReg_32_XM0RegClass ||
  759       RegClass == &AMDGPU::SReg_32_XM0RegClass ||
 1074       MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
 1199       MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
 4037       Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 4043       Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 4069     Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 4141       Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 4147       Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 5269   Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 5270   Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);

lib/Target/AMDGPU/SIRegisterInfo.cpp

  362   Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
 1100           RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);
 1141                 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MIB, 0, false);
 1161                 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);

lib/Target/AMDGPU/SIWholeQuadMode.cpp

  559   Register SaveReg = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);