reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

17336   extern const TargetRegisterClass SReg_32RegClass;

References

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

19669   &AMDGPU::SReg_32RegClass,
19676   &AMDGPU::SReg_32RegClass,
19684   &AMDGPU::SReg_32RegClass,
19695   &AMDGPU::SReg_32RegClass,
19707   &AMDGPU::SReg_32RegClass,
19720   &AMDGPU::SReg_32RegClass,
19738   &AMDGPU::SReg_32RegClass,
21721     &AMDGPU::SReg_32RegClass,

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

  768         if (AMDGPU::SReg_32RegClass.contains(Reg)) {

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  346     = IsSALU ? AMDGPU::SReg_32RegClass : AMDGPU::VGPR_32RegClass;
  426     MRI.setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass);
  428   if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, MRI) ||
  429       !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, MRI) ||
  430       !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, MRI))
  737         RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
 1241         DstSize > 32 ? &AMDGPU::SReg_64RegClass : &AMDGPU::SReg_32RegClass;
 1245     Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
 1302     if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, *MRI))
 1311       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);
 1321       Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
 1349     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);
 1443       &AMDGPU::SReg_32RegClass : &AMDGPU::VGPR_32RegClass;
 1609     DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI);
 1627     = IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass;
 1940   Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 1161     Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);

lib/Target/AMDGPU/SIISelLowering.cpp

  120   addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
  146     addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
  147     addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
  150     addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
  151     addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
 1998     else if (AMDGPU::SReg_32RegClass.contains(*I))
 2349         else if (AMDGPU::SReg_32RegClass.contains(*I))
 3610     Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
 3611     Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
 3615      &AMDGPU::SReg_32RegClass);
 3618       &AMDGPU::SReg_32RegClass);
 3622       &AMDGPU::SReg_32RegClass);
 3625       &AMDGPU::SReg_32RegClass);
10555         RC = &AMDGPU::SReg_32RegClass;
10942                                                : &AMDGPU::SReg_32RegClass;

lib/Target/AMDGPU/SIInstrInfo.cpp

  532            AMDGPU::SReg_32RegClass.contains(SrcReg) ||
  542       RC == &AMDGPU::SReg_32RegClass) {
  551       if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
  565     if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
  602     assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
  611            AMDGPU::SReg_32RegClass.contains(SrcReg) ||
  757   if (RegClass == &AMDGPU::SReg_32RegClass ||
 3127     return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
 5195     Register Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
 5196     Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
 5240   Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
 5241   Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

  911     Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
 1004     Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
 1360   Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);

lib/Target/AMDGPU/SILowerI1Copies.cpp

  430   return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass
  570     MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
  691       MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1249     &AMDGPU::SReg_32RegClass,
 1788       return &AMDGPU::SReg_32RegClass;
 1803                                                  &AMDGPU::SReg_32RegClass;
 1828                                                    &AMDGPU::SReg_32RegClass;

lib/Target/AMDGPU/SIRegisterInfo.h

  266     return isWave32 ? &AMDGPU::SReg_32RegClass