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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15505 static const MCOperandInfo OperandInfo163[] = { { AMDGPU::SReg_1_XEXECRegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15621 static const MCOperandInfo OperandInfo279[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_1RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_1_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15685 static const MCOperandInfo OperandInfo343[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_1_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 72 (1u << (AMDGPU::SReg_1_XEXECRegClassID - 0)) |
163 (1u << (AMDGPU::SReg_1_XEXECRegClassID - 0)) |
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11245 { SReg_1_XEXEC, SReg_1_XEXECBits, 3290, 207, sizeof(SReg_1_XEXECBits), AMDGPU::SReg_1_XEXECRegClassID, 1, false },
20360 &AMDGPUMCRegisterClasses[SReg_1_XEXECRegClassID],
lib/Target/AMDGPU/SIISelLowering.cpp 3285 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3761 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
lib/Target/AMDGPU/SIInstrInfo.cpp 822 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4332 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4413 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4702 const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5347 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 1390 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
lib/Target/AMDGPU/SIRegisterInfo.cpp 1853 case AMDGPU::SReg_1_XEXECRegClassID: