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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15745 static const MCOperandInfo OperandInfo403[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15745 static const MCOperandInfo OperandInfo403[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15746 static const MCOperandInfo OperandInfo404[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15746 static const MCOperandInfo OperandInfo404[] = { { AMDGPU::AReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_512RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15748 static const MCOperandInfo OperandInfo406[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15748 static const MCOperandInfo OperandInfo406[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15749 static const MCOperandInfo OperandInfo407[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15749 static const MCOperandInfo OperandInfo407[] = { { AMDGPU::AReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_128RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15750 static const MCOperandInfo OperandInfo408[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15750 static const MCOperandInfo OperandInfo408[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15751 static const MCOperandInfo OperandInfo409[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15751 static const MCOperandInfo OperandInfo409[] = { { AMDGPU::AReg_1024RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AV_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AReg_1024RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_AC_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 194 (1u << (AMDGPU::AV_32RegClassID - 0)) |
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11251 { AV_32, AV_32Bits, 276, 512, sizeof(AV_32Bits), AMDGPU::AV_32RegClassID, 1, false },
20432 &AMDGPUMCRegisterClasses[AV_32RegClassID],
lib/Target/AMDGPU/SIISelLowering.cpp10408 OpInfo[I].RegClass != llvm::AMDGPU::AV_32RegClassID) ||
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1086 case AMDGPU::AV_32RegClassID: