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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15512 static const MCOperandInfo OperandInfo170[] = { { AMDGPU::AGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15513 static const MCOperandInfo OperandInfo171[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::AGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
15616 static const MCOperandInfo OperandInfo274[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::AGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
15617 static const MCOperandInfo OperandInfo275[] = { { AMDGPU::AGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc11254 { AGPR_32, AGPR_32Bits, 216, 256, sizeof(AGPR_32Bits), AMDGPU::AGPR_32RegClassID, 1, true },
20468 &AMDGPUMCRegisterClasses[AGPR_32RegClassID],
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 537 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32);
541 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16);
549 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32);
553 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16);
1928 case 1: return AMDGPU::AGPR_32RegClassID;
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 707 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
941 return AGPR_32RegClassID;
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 421 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1084 case AMDGPU::AGPR_32RegClassID: