reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc
37412     CEFBS_HasDPP_HasDPP, // V_ADDC_U32_dpp = 2320
37420     CEFBS_HasDPP_HasDPP, // V_ADD_F32_dpp = 2328
37426     CEFBS_HasDPP_HasDPP, // V_ADD_I32_dpp = 2334
37442     CEFBS_HasDPP_HasDPP, // V_AND_B32_dpp = 2350
37451     CEFBS_HasDPP_HasDPP, // V_ASHRREV_I32_dpp = 2359
37468     CEFBS_HasDPP_HasDPP, // V_BFREV_B32_dpp = 2376
37476     CEFBS_HasDPP_HasDPP, // V_CEIL_F32_dpp = 2384
38516     CEFBS_HasDPP_HasDPP, // V_CNDMASK_B32_dpp = 3424
38525     CEFBS_HasDPP_HasDPP, // V_COS_F32_dpp = 3433
38533     CEFBS_HasDPP_HasDPP, // V_CVT_F16_F32_dpp = 3441
38545     CEFBS_HasDPP_HasDPP, // V_CVT_F32_F16_dpp = 3453
38551     CEFBS_HasDPP_HasDPP, // V_CVT_F32_I32_dpp = 3459
38555     CEFBS_HasDPP_HasDPP, // V_CVT_F32_U32_dpp = 3463
38559     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE0_dpp = 3467
38563     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE1_dpp = 3471
38567     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE2_dpp = 3475
38571     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE3_dpp = 3479
38581     CEFBS_HasDPP_HasDPP, // V_CVT_FLR_I32_F32_dpp = 3489
38589     CEFBS_HasDPP_HasDPP, // V_CVT_I32_F32_dpp = 3497
38603     CEFBS_HasDPP_HasDPP, // V_CVT_OFF_F32_I4_dpp = 3511
38622     CEFBS_HasDPP_HasDPP, // V_CVT_RPI_I32_F32_dpp = 3530
38630     CEFBS_HasDPP_HasDPP, // V_CVT_U32_F32_dpp = 3538
38667     CEFBS_HasDPP_HasDPP, // V_EXP_F32_dpp = 3575
38675     CEFBS_HasDPP_HasDPP, // V_FFBH_I32_dpp = 3583
38679     CEFBS_HasDPP_HasDPP, // V_FFBH_U32_dpp = 3587
38683     CEFBS_HasDPP_HasDPP, // V_FFBL_B32_dpp = 3591
38691     CEFBS_HasDPP_HasDPP, // V_FLOOR_F32_dpp = 3599
38720     CEFBS_HasDPP_HasDPP, // V_FRACT_F32_dpp = 3628
38730     CEFBS_HasDPP_HasDPP, // V_FREXP_EXP_I32_F32_dpp = 3638
38740     CEFBS_HasDPP_HasDPP, // V_FREXP_MANT_F32_dpp = 3648
38773     CEFBS_HasDPP_HasDPP, // V_LOG_F32_dpp = 3681
38785     CEFBS_HasDPP_HasDPP, // V_LSHLREV_B32_dpp = 3693
38801     CEFBS_HasDPP_HasDPP, // V_LSHRREV_B32_dpp = 3709
38815     CEFBS_HasDPP_HasDPP, // V_MAC_F32_dpp = 3723
38854     CEFBS_HasDPP_HasDPP, // V_MAX_F32_dpp = 3762
38863     CEFBS_HasDPP_HasDPP, // V_MAX_I32_dpp = 3771
38875     CEFBS_HasDPP_HasDPP, // V_MAX_U32_dpp = 3783
38919     CEFBS_HasDPP_HasDPP, // V_MIN_F32_dpp = 3827
38928     CEFBS_HasDPP_HasDPP, // V_MIN_I32_dpp = 3836
38940     CEFBS_HasDPP_HasDPP, // V_MIN_U32_dpp = 3848
38957     CEFBS_HasDPP_HasDPP, // V_MOV_B32_dpp = 3865
38962     CEFBS_HasDPP_HasDPP, // V_MOV_B64_DPP_PSEUDO = 3870
38964     CEFBS_HasDPP_HasDPP, // V_MOV_FED_B32_dpp = 3872
38976     CEFBS_HasDPP_HasDPP, // V_MUL_F32_dpp = 3884
38982     CEFBS_HasDPP_HasDPP, // V_MUL_HI_I32_I24_dpp = 3890
38987     CEFBS_HasDPP_HasDPP, // V_MUL_HI_U32_U24_dpp = 3895
38991     CEFBS_HasDPP_HasDPP, // V_MUL_I32_I24_dpp = 3899
38995     CEFBS_HasDPP_HasDPP, // V_MUL_LEGACY_F32_dpp = 3903
39005     CEFBS_HasDPP_HasDPP, // V_MUL_U32_U24_dpp = 3913
39012     CEFBS_HasDPP_HasDPP, // V_NOT_B32_dpp = 3920
39017     CEFBS_HasDPP_HasDPP, // V_OR_B32_dpp = 3925
39062     CEFBS_HasDPP_HasDPP, // V_RCP_F32_dpp = 3970
39068     CEFBS_HasDPP_HasDPP, // V_RCP_IFLAG_F32_dpp = 3976
39081     CEFBS_HasDPP_HasDPP, // V_RNDNE_F32_dpp = 3989
39097     CEFBS_HasDPP_HasDPP, // V_RSQ_F32_dpp = 4005
39125     CEFBS_HasDPP_HasDPP, // V_SIN_F32_dpp = 4033
39133     CEFBS_HasDPP_HasDPP, // V_SQRT_F32_dpp = 4041
39139     CEFBS_HasDPP_HasDPP, // V_SUBBREV_U32_dpp = 4047
39143     CEFBS_HasDPP_HasDPP, // V_SUBB_U32_dpp = 4051
39151     CEFBS_HasDPP_HasDPP, // V_SUBREV_F32_dpp = 4059
39155     CEFBS_HasDPP_HasDPP, // V_SUBREV_I32_dpp = 4063
39171     CEFBS_HasDPP_HasDPP, // V_SUB_F32_dpp = 4079
39176     CEFBS_HasDPP_HasDPP, // V_SUB_I32_dpp = 4084
39196     CEFBS_HasDPP_HasDPP, // V_TRUNC_F32_dpp = 4104
39209     CEFBS_HasDPP_HasDPP, // V_XOR_B32_dpp = 4117
47032     CEFBS_HasDPP_HasDPP, // V_ADD_F32_dpp_vi = 11940
47080     CEFBS_HasDPP_HasDPP, // V_AND_B32_dpp_vi = 11988
47100     CEFBS_HasDPP_HasDPP, // V_ASHRREV_I32_dpp_vi = 12008
47134     CEFBS_HasDPP_HasDPP, // V_BFREV_B32_dpp_vi = 12042
47156     CEFBS_HasDPP_HasDPP, // V_CEIL_F32_dpp_vi = 12064
48738     CEFBS_HasDPP_HasDPP, // V_CNDMASK_B32_dpp_vi = 13646
48764     CEFBS_HasDPP_HasDPP, // V_COS_F32_dpp_vi = 13672
48788     CEFBS_HasDPP_HasDPP, // V_CVT_F16_F32_dpp_vi = 13696
48820     CEFBS_HasDPP_HasDPP, // V_CVT_F32_F16_dpp_vi = 13728
48838     CEFBS_HasDPP_HasDPP, // V_CVT_F32_I32_dpp_vi = 13746
48850     CEFBS_HasDPP_HasDPP, // V_CVT_F32_U32_dpp_vi = 13758
48862     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE0_dpp_vi = 13770
48874     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE1_dpp_vi = 13782
48886     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE2_dpp_vi = 13794
48898     CEFBS_HasDPP_HasDPP, // V_CVT_F32_UBYTE3_dpp_vi = 13806
48928     CEFBS_HasDPP_HasDPP, // V_CVT_FLR_I32_F32_dpp_vi = 13836
48950     CEFBS_HasDPP_HasDPP, // V_CVT_I32_F32_dpp_vi = 13858
48988     CEFBS_HasDPP_HasDPP, // V_CVT_OFF_F32_I4_dpp_vi = 13896
49031     CEFBS_HasDPP_HasDPP, // V_CVT_RPI_I32_F32_dpp_vi = 13939
49053     CEFBS_HasDPP_HasDPP, // V_CVT_U32_F32_dpp_vi = 13961
49131     CEFBS_HasDPP_HasDPP, // V_EXP_F32_dpp_vi = 14039
49150     CEFBS_HasDPP_HasDPP, // V_FFBH_I32_dpp_vi = 14058
49162     CEFBS_HasDPP_HasDPP, // V_FFBH_U32_dpp_vi = 14070
49174     CEFBS_HasDPP_HasDPP, // V_FFBL_B32_dpp_vi = 14082
49196     CEFBS_HasDPP_HasDPP, // V_FLOOR_F32_dpp_vi = 14104
49256     CEFBS_HasDPP_HasDPP, // V_FRACT_F32_dpp_vi = 14164
49284     CEFBS_HasDPP_HasDPP, // V_FREXP_EXP_I32_F32_dpp_vi = 14192
49312     CEFBS_HasDPP_HasDPP, // V_FREXP_MANT_F32_dpp_vi = 14220
49388     CEFBS_HasDPP_HasDPP, // V_LOG_F32_dpp_vi = 14296
49413     CEFBS_HasDPP_HasDPP, // V_LSHLREV_B32_dpp_vi = 14321
49440     CEFBS_HasDPP_HasDPP, // V_LSHRREV_B32_dpp_vi = 14348
49461     CEFBS_HasDPP_HasDPP, // V_MAC_F32_dpp_vi = 14369
49547     CEFBS_HasDPP_HasDPP, // V_MAX_F32_dpp_vi = 14455
49568     CEFBS_HasDPP_HasDPP, // V_MAX_I32_dpp_vi = 14476
49588     CEFBS_HasDPP_HasDPP, // V_MAX_U32_dpp_vi = 14496
49668     CEFBS_HasDPP_HasDPP, // V_MIN_F32_dpp_vi = 14576
49689     CEFBS_HasDPP_HasDPP, // V_MIN_I32_dpp_vi = 14597
49709     CEFBS_HasDPP_HasDPP, // V_MIN_U32_dpp_vi = 14617
49741     CEFBS_HasDPP_HasDPP, // V_MOV_B32_dpp_vi = 14649
49753     CEFBS_HasDPP_HasDPP, // V_MOV_FED_B32_dpp_vi = 14661
49786     CEFBS_HasDPP_HasDPP, // V_MUL_F32_dpp_vi = 14694
49801     CEFBS_HasDPP_HasDPP, // V_MUL_HI_I32_I24_dpp_vi = 14709
49816     CEFBS_HasDPP_HasDPP, // V_MUL_HI_U32_U24_dpp_vi = 14724
49831     CEFBS_HasDPP_HasDPP, // V_MUL_I32_I24_dpp_vi = 14739
49843     CEFBS_HasDPP_HasDPP, // V_MUL_LEGACY_F32_dpp_vi = 14751
49867     CEFBS_HasDPP_HasDPP, // V_MUL_U32_U24_dpp_vi = 14775
49888     CEFBS_HasDPP_HasDPP, // V_NOT_B32_dpp_vi = 14796
49902     CEFBS_HasDPP_HasDPP, // V_OR_B32_dpp_vi = 14810
49980     CEFBS_HasDPP_HasDPP, // V_RCP_F32_dpp_vi = 14888
49998     CEFBS_HasDPP_HasDPP, // V_RCP_IFLAG_F32_dpp_vi = 14906
50026     CEFBS_HasDPP_HasDPP, // V_RNDNE_F32_dpp_vi = 14934
50058     CEFBS_HasDPP_HasDPP, // V_RSQ_F32_dpp_vi = 14966
50114     CEFBS_HasDPP_HasDPP, // V_SIN_F32_dpp_vi = 15022
50136     CEFBS_HasDPP_HasDPP, // V_SQRT_F32_dpp_vi = 15044
50200     CEFBS_HasDPP_HasDPP, // V_SUBREV_F32_dpp_vi = 15108
50258     CEFBS_HasDPP_HasDPP, // V_SUB_F32_dpp_vi = 15166
50311     CEFBS_HasDPP_HasDPP, // V_TRUNC_F32_dpp_vi = 15219
50345     CEFBS_HasDPP_HasDPP, // V_XOR_B32_dpp_vi = 15253