reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
177 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
lib/Target/AMDGPU/SIFoldOperands.cpp 178 OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(), AMDGPU::OpName::vaddr);
lib/Target/AMDGPU/SIInstrInfo.cpp216 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || 324 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); 341 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); 373 const MachineOperand *VAddr = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); 4694 MachineOperand *VAddr = getNamedOperand(MI, AMDGPU::OpName::vaddr); 5921 const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
322 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) == -1) 492 AddrOpName[NumAddresses++] = AMDGPU::OpName::vaddr; 1159 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); 1325 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); 1432 TII->getNamedOperand(MI, AMDGPU::OpName::vaddr)->setReg(NewBase); 1541 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); 1604 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr);lib/Target/AMDGPU/SILowerSGPRSpills.cpp
279 AMDGPU::OpName::vaddr);
lib/Target/AMDGPU/SIRegisterInfo.cpp327 AMDGPU::OpName::vaddr) && 394 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); 1204 AMDGPU::OpName::vaddr));