|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc21375 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21376 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
21377 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
22725 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
22726 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23034 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23035 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23515 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23516 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
23859 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
23860 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32 }, },
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc55897 case AMDGPU::V_SUB_CO_U32_e32_gfx9:
97343 { AMDGPU::V_SUB_I32_e32, AMDGPU::V_SUB_I32_e32_gfx6_gfx7, AMDGPU::V_SUB_U32_e32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::V_SUB_CO_U32_e32_gfx9, (uint16_t)-1U, (uint16_t)-1U },
gen/lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc33800 case AMDGPU::V_SUB_CO_U32_e32_gfx9: