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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc21388 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21389 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21390 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22744 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22745 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23040 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23041 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23525 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23526 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23873 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23874 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc55880 case AMDGPU::V_SUBB_CO_U32_e32_gfx9:
97310 { AMDGPU::V_SUBB_U32_e32, AMDGPU::V_SUBB_U32_e32_gfx6_gfx7, AMDGPU::V_SUBB_U32_e32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::V_SUBB_CO_U32_e32_gfx9, AMDGPU::V_SUB_CO_CI_U32_e32_gfx10, (uint16_t)-1U },
gen/lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc33784 case AMDGPU::V_SUBB_CO_U32_e32_gfx9: