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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc18867 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18868 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
18869 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
21467 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
21468 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
22801 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
22802 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23076 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23077 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
23579 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC }, },
23580 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, AMFBS_isGFX9Only_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VSrcB32, MCK_VGPR_32, MCK_VCC_LO }, },
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc55667 case AMDGPU::V_ADDC_CO_U32_e32_gfx9:
95744 { AMDGPU::V_ADDC_U32_e32, AMDGPU::V_ADDC_U32_e32_gfx6_gfx7, AMDGPU::V_ADDC_U32_e32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::V_ADDC_CO_U32_e32_gfx9, AMDGPU::V_ADD_CO_CI_U32_e32_gfx10, (uint16_t)-1U },
gen/lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc33661 case AMDGPU::V_ADDC_CO_U32_e32_gfx9: