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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc55196 case AMDGPU::V_ACCVGPR_WRITE_B32:
95741 { AMDGPU::V_ACCVGPR_WRITE_B32, (uint16_t)-1U, AMDGPU::V_ACCVGPR_WRITE_B32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U },
lib/Target/AMDGPU/AMDGPUSubtarget.cpp 862 MAI.getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32 ||
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 1235 MI->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32 &&
1243 if (Op.isDef() && Opc != AMDGPU::V_ACCVGPR_WRITE_B32)
1287 } else if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32) {
1306 if (MI->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32)
1329 if (Opc == AMDGPU::V_ACCVGPR_WRITE_B32) {
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 308 AMDGPU::V_ACCVGPR_WRITE_B32 : AMDGPU::COPY;
lib/Target/AMDGPU/SIFoldOperands.cpp 646 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
709 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addImm(Imm);
751 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addReg(Vgpr);
765 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
lib/Target/AMDGPU/SIInstrInfo.cpp 619 if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32)
639 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
671 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
676 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
699 AMDGPU::V_ACCVGPR_WRITE_B32 : AMDGPU::COPY;
2267 case AMDGPU::V_ACCVGPR_WRITE_B32:
2321 case AMDGPU::V_ACCVGPR_WRITE_B32:
2338 NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32;
lib/Target/AMDGPU/SIRegisterInfo.cpp 565 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32
728 MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32),