reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  576   case AMDGPU::REG_SEQUENCE: {
  711   CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
 1030   SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
 1717       Addr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
 1799   return SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, SL, MVT::i64,

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  382   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
 1323       BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg)
 1453     ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
 1664   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)

lib/Target/AMDGPU/GCNDPPCombine.cpp

  458     if (OrigOp == AMDGPU::REG_SEQUENCE) {

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  663       case AMDGPU::REG_SEQUENCE:

lib/Target/AMDGPU/SIFixupVectorISel.cpp

  103     case AMDGPU::REG_SEQUENCE:

lib/Target/AMDGPU/SIFoldOperands.cpp

  693         UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE));

lib/Target/AMDGPU/SIISelLowering.cpp

 3779     BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
10304       Opcode == AMDGPU::REG_SEQUENCE) {
10486   SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
10498   return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
10532   return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);

lib/Target/AMDGPU/SIInstrInfo.cpp

 1611     BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
 2229     MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
 3730   case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
 3730   case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
 4245               get(AMDGPU::REG_SEQUENCE), DstReg);
 4359   BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
 4502   BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc)
 4595   if (MI.getOpcode() == AMDGPU::REG_SEQUENCE) {
 4726       BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
 4802       BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
 5631     case AMDGPU::REG_SEQUENCE:
 5744   case AMDGPU::REG_SEQUENCE:
 5756       case AMDGPU::REG_SEQUENCE:
 6397   case AMDGPU::REG_SEQUENCE:

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

 1313   BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg)
 1468   if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE