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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17123 { 1061, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1061 = DS_CMPST_RTN_B32
17124 { 1062, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1062 = DS_CMPST_RTN_B32_gfx9
17127 { 1065, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1065 = DS_CMPST_RTN_F32
17128 { 1066, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1066 = DS_CMPST_RTN_F32_gfx9
17224 { 1162, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1162 = DS_MSKOR_RTN_B32
17225 { 1163, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1163 = DS_MSKOR_RTN_B32_gfx9
17293 { 1231, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1231 = DS_WRAP_RTN_B32
17294 { 1232, 6, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1232 = DS_WRAP_RTN_B32_gfx9
21589 { 5527, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5527 = DS_CMPST_RTN_B32_gfx10
21590 { 5528, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5528 = DS_CMPST_RTN_B32_gfx6_gfx7
21591 { 5529, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5529 = DS_CMPST_RTN_B32_vi
21595 { 5533, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5533 = DS_CMPST_RTN_F32_gfx10
21596 { 5534, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5534 = DS_CMPST_RTN_F32_gfx6_gfx7
21597 { 5535, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5535 = DS_CMPST_RTN_F32_vi
21775 { 5713, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5713 = DS_MSKOR_RTN_B32_gfx10
21776 { 5714, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5714 = DS_MSKOR_RTN_B32_gfx6_gfx7
21777 { 5715, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5715 = DS_MSKOR_RTN_B32_vi
21896 { 5834, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5834 = DS_WRAP_RTN_B32_gfx10
21897 { 5835, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5835 = DS_WRAP_RTN_B32_gfx7
21898 { 5836, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #5836 = DS_WRAP_RTN_B32_vi