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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17094 { 1032, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1032 = DS_ADD_RTN_U64
17095 { 1033, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1033 = DS_ADD_RTN_U64_gfx9
17109 { 1047, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1047 = DS_AND_RTN_B64
17110 { 1048, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1048 = DS_AND_RTN_B64_gfx9
17131 { 1069, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1069 = DS_CONDXCHG32_RTN_B64
17132 { 1070, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1070 = DS_CONDXCHG32_RTN_B64_gfx9
17136 { 1074, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1074 = DS_DEC_RTN_U64
17137 { 1075, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1075 = DS_DEC_RTN_U64_gfx9
17152 { 1090, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1090 = DS_INC_RTN_U64
17153 { 1091, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1091 = DS_INC_RTN_U64_gfx9
17170 { 1108, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1108 = DS_MAX_RTN_F64
17171 { 1109, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1109 = DS_MAX_RTN_F64_gfx9
17174 { 1112, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1112 = DS_MAX_RTN_I64
17175 { 1113, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1113 = DS_MAX_RTN_I64_gfx9
17178 { 1116, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1116 = DS_MAX_RTN_U64
17179 { 1117, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1117 = DS_MAX_RTN_U64_gfx9
17200 { 1138, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1138 = DS_MIN_RTN_F64
17201 { 1139, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1139 = DS_MIN_RTN_F64_gfx9
17204 { 1142, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1142 = DS_MIN_RTN_I64
17205 { 1143, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1143 = DS_MIN_RTN_I64_gfx9
17208 { 1146, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1146 = DS_MIN_RTN_U64
17209 { 1147, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1147 = DS_MIN_RTN_U64_gfx9
17236 { 1174, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1174 = DS_OR_RTN_B64
17237 { 1175, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1175 = DS_OR_RTN_B64_gfx9
17274 { 1212, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1212 = DS_RSUB_RTN_U64
17275 { 1213, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1213 = DS_RSUB_RTN_U64_gfx9
17284 { 1222, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1222 = DS_SUB_RTN_U64
17285 { 1223, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1223 = DS_SUB_RTN_U64_gfx9
17330 { 1268, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1268 = DS_WRXCHG_RTN_B64
17331 { 1269, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1269 = DS_WRXCHG_RTN_B64_gfx9
17338 { 1276, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1276 = DS_XOR_RTN_B64
17339 { 1277, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #1277 = DS_XOR_RTN_B64_gfx9
21537 { 5475, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5475 = DS_ADD_RTN_U64_gfx10
21538 { 5476, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5476 = DS_ADD_RTN_U64_gfx6_gfx7
21539 { 5477, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5477 = DS_ADD_RTN_U64_vi
21563 { 5501, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5501 = DS_AND_RTN_B64_gfx10
21564 { 5502, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5502 = DS_AND_RTN_B64_gfx6_gfx7
21565 { 5503, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5503 = DS_AND_RTN_B64_vi
21601 { 5539, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5539 = DS_CONDXCHG32_RTN_B64_gfx10
21602 { 5540, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5540 = DS_CONDXCHG32_RTN_B64_gfx7
21603 { 5541, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5541 = DS_CONDXCHG32_RTN_B64_vi
21610 { 5548, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5548 = DS_DEC_RTN_U64_gfx10
21611 { 5549, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5549 = DS_DEC_RTN_U64_gfx6_gfx7
21612 { 5550, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5550 = DS_DEC_RTN_U64_vi
21646 { 5584, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5584 = DS_INC_RTN_U64_gfx10
21647 { 5585, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5585 = DS_INC_RTN_U64_gfx6_gfx7
21648 { 5586, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5586 = DS_INC_RTN_U64_vi
21676 { 5614, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5614 = DS_MAX_RTN_F64_gfx10
21677 { 5615, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5615 = DS_MAX_RTN_F64_gfx6_gfx7
21678 { 5616, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5616 = DS_MAX_RTN_F64_vi
21682 { 5620, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5620 = DS_MAX_RTN_I64_gfx10
21683 { 5621, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5621 = DS_MAX_RTN_I64_gfx6_gfx7
21684 { 5622, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5622 = DS_MAX_RTN_I64_vi
21688 { 5626, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5626 = DS_MAX_RTN_U64_gfx10
21689 { 5627, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5627 = DS_MAX_RTN_U64_gfx6_gfx7
21690 { 5628, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5628 = DS_MAX_RTN_U64_vi
21730 { 5668, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5668 = DS_MIN_RTN_F64_gfx10
21731 { 5669, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5669 = DS_MIN_RTN_F64_gfx6_gfx7
21732 { 5670, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5670 = DS_MIN_RTN_F64_vi
21736 { 5674, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5674 = DS_MIN_RTN_I64_gfx10
21737 { 5675, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5675 = DS_MIN_RTN_I64_gfx6_gfx7
21738 { 5676, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5676 = DS_MIN_RTN_I64_vi
21742 { 5680, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5680 = DS_MIN_RTN_U64_gfx10
21743 { 5681, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5681 = DS_MIN_RTN_U64_gfx6_gfx7
21744 { 5682, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5682 = DS_MIN_RTN_U64_vi
21796 { 5734, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5734 = DS_OR_RTN_B64_gfx10
21797 { 5735, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5735 = DS_OR_RTN_B64_gfx6_gfx7
21798 { 5736, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5736 = DS_OR_RTN_B64_vi
21860 { 5798, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5798 = DS_RSUB_RTN_U64_gfx10
21861 { 5799, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5799 = DS_RSUB_RTN_U64_gfx6_gfx7
21862 { 5800, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5800 = DS_RSUB_RTN_U64_vi
21878 { 5816, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5816 = DS_SUB_RTN_U64_gfx10
21879 { 5817, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5817 = DS_SUB_RTN_U64_gfx6_gfx7
21880 { 5818, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5818 = DS_SUB_RTN_U64_vi
21956 { 5894, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5894 = DS_WRXCHG_RTN_B64_gfx10
21957 { 5895, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5895 = DS_WRXCHG_RTN_B64_gfx6_gfx7
21958 { 5896, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5896 = DS_WRXCHG_RTN_B64_vi
21968 { 5906, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5906 = DS_XOR_RTN_B64_gfx10
21969 { 5907, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5907 = DS_XOR_RTN_B64_gfx6_gfx7
21970 { 5908, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #5908 = DS_XOR_RTN_B64_vi