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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17090 { 1028, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1028 = DS_ADD_RTN_F32
17091 { 1029, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1029 = DS_ADD_RTN_F32_gfx9
17092 { 1030, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1030 = DS_ADD_RTN_U32
17093 { 1031, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1031 = DS_ADD_RTN_U32_gfx9
17107 { 1045, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1045 = DS_AND_RTN_B32
17108 { 1046, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1046 = DS_AND_RTN_B32_gfx9
17115 { 1053, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1053 = DS_CMPST_B32
17116 { 1054, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1054 = DS_CMPST_B32_gfx9
17119 { 1057, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1057 = DS_CMPST_F32
17120 { 1058, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1058 = DS_CMPST_F32_gfx9
17134 { 1072, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1072 = DS_DEC_RTN_U32
17135 { 1073, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1073 = DS_DEC_RTN_U32_gfx9
17150 { 1088, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1088 = DS_INC_RTN_U32
17151 { 1089, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1089 = DS_INC_RTN_U32_gfx9
17168 { 1106, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1106 = DS_MAX_RTN_F32
17169 { 1107, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1107 = DS_MAX_RTN_F32_gfx9
17172 { 1110, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1110 = DS_MAX_RTN_I32
17173 { 1111, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1111 = DS_MAX_RTN_I32_gfx9
17176 { 1114, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1114 = DS_MAX_RTN_U32
17177 { 1115, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1115 = DS_MAX_RTN_U32_gfx9
17198 { 1136, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1136 = DS_MIN_RTN_F32
17199 { 1137, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1137 = DS_MIN_RTN_F32_gfx9
17202 { 1140, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1140 = DS_MIN_RTN_I32
17203 { 1141, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1141 = DS_MIN_RTN_I32_gfx9
17206 { 1144, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1144 = DS_MIN_RTN_U32
17207 { 1145, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1145 = DS_MIN_RTN_U32_gfx9
17220 { 1158, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1158 = DS_MSKOR_B32
17221 { 1159, 5, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1159 = DS_MSKOR_B32_gfx9
17234 { 1172, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1172 = DS_OR_RTN_B32
17235 { 1173, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1173 = DS_OR_RTN_B32_gfx9
17272 { 1210, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1210 = DS_RSUB_RTN_U32
17273 { 1211, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1211 = DS_RSUB_RTN_U32_gfx9
17282 { 1220, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1220 = DS_SUB_RTN_U32
17283 { 1221, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1221 = DS_SUB_RTN_U32_gfx9
17328 { 1266, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1266 = DS_WRXCHG_RTN_B32
17329 { 1267, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1267 = DS_WRXCHG_RTN_B32_gfx9
17336 { 1274, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1274 = DS_XOR_RTN_B32
17337 { 1275, 5, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #1275 = DS_XOR_RTN_B32_gfx9
21532 { 5470, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5470 = DS_ADD_RTN_F32_gfx10
21533 { 5471, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5471 = DS_ADD_RTN_F32_vi
21534 { 5472, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5472 = DS_ADD_RTN_U32_gfx10
21535 { 5473, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5473 = DS_ADD_RTN_U32_gfx6_gfx7
21536 { 5474, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5474 = DS_ADD_RTN_U32_vi
21560 { 5498, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5498 = DS_AND_RTN_B32_gfx10
21561 { 5499, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5499 = DS_AND_RTN_B32_gfx6_gfx7
21562 { 5500, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5500 = DS_AND_RTN_B32_vi
21577 { 5515, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5515 = DS_CMPST_B32_gfx10
21578 { 5516, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5516 = DS_CMPST_B32_gfx6_gfx7
21579 { 5517, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5517 = DS_CMPST_B32_vi
21583 { 5521, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5521 = DS_CMPST_F32_gfx10
21584 { 5522, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5522 = DS_CMPST_F32_gfx6_gfx7
21585 { 5523, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5523 = DS_CMPST_F32_vi
21607 { 5545, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5545 = DS_DEC_RTN_U32_gfx10
21608 { 5546, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5546 = DS_DEC_RTN_U32_gfx6_gfx7
21609 { 5547, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5547 = DS_DEC_RTN_U32_vi
21643 { 5581, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5581 = DS_INC_RTN_U32_gfx10
21644 { 5582, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5582 = DS_INC_RTN_U32_gfx6_gfx7
21645 { 5583, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5583 = DS_INC_RTN_U32_vi
21673 { 5611, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5611 = DS_MAX_RTN_F32_gfx10
21674 { 5612, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5612 = DS_MAX_RTN_F32_gfx6_gfx7
21675 { 5613, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5613 = DS_MAX_RTN_F32_vi
21679 { 5617, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5617 = DS_MAX_RTN_I32_gfx10
21680 { 5618, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5618 = DS_MAX_RTN_I32_gfx6_gfx7
21681 { 5619, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5619 = DS_MAX_RTN_I32_vi
21685 { 5623, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5623 = DS_MAX_RTN_U32_gfx10
21686 { 5624, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5624 = DS_MAX_RTN_U32_gfx6_gfx7
21687 { 5625, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5625 = DS_MAX_RTN_U32_vi
21727 { 5665, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5665 = DS_MIN_RTN_F32_gfx10
21728 { 5666, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5666 = DS_MIN_RTN_F32_gfx6_gfx7
21729 { 5667, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5667 = DS_MIN_RTN_F32_vi
21733 { 5671, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5671 = DS_MIN_RTN_I32_gfx10
21734 { 5672, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5672 = DS_MIN_RTN_I32_gfx6_gfx7
21735 { 5673, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5673 = DS_MIN_RTN_I32_vi
21739 { 5677, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5677 = DS_MIN_RTN_U32_gfx10
21740 { 5678, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5678 = DS_MIN_RTN_U32_gfx6_gfx7
21741 { 5679, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5679 = DS_MIN_RTN_U32_vi
21769 { 5707, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5707 = DS_MSKOR_B32_gfx10
21770 { 5708, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5708 = DS_MSKOR_B32_gfx6_gfx7
21771 { 5709, 5, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5709 = DS_MSKOR_B32_vi
21793 { 5731, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5731 = DS_OR_RTN_B32_gfx10
21794 { 5732, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5732 = DS_OR_RTN_B32_gfx6_gfx7
21795 { 5733, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5733 = DS_OR_RTN_B32_vi
21857 { 5795, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5795 = DS_RSUB_RTN_U32_gfx10
21858 { 5796, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5796 = DS_RSUB_RTN_U32_gfx6_gfx7
21859 { 5797, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5797 = DS_RSUB_RTN_U32_vi
21875 { 5813, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5813 = DS_SUB_RTN_U32_gfx10
21876 { 5814, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5814 = DS_SUB_RTN_U32_gfx6_gfx7
21877 { 5815, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5815 = DS_SUB_RTN_U32_vi
21953 { 5891, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5891 = DS_WRXCHG_RTN_B32_gfx10
21954 { 5892, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5892 = DS_WRXCHG_RTN_B32_gfx6_gfx7
21955 { 5893, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5893 = DS_WRXCHG_RTN_B32_vi
21965 { 5903, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5903 = DS_XOR_RTN_B32_gfx10
21966 { 5904, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5904 = DS_XOR_RTN_B32_gfx6_gfx7
21967 { 5905, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #5905 = DS_XOR_RTN_B32_vi