|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc17088 { 1026, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1026 = DS_ADD_F32
17089 { 1027, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1027 = DS_ADD_F32_gfx9
17099 { 1037, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1037 = DS_ADD_U32
17100 { 1038, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1038 = DS_ADD_U32_gfx9
17103 { 1041, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1041 = DS_AND_B32
17104 { 1042, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1042 = DS_AND_B32_gfx9
17140 { 1078, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1078 = DS_DEC_U32
17141 { 1079, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1079 = DS_DEC_U32_gfx9
17156 { 1094, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1094 = DS_INC_U32
17157 { 1095, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1095 = DS_INC_U32_gfx9
17160 { 1098, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1098 = DS_MAX_F32
17161 { 1099, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1099 = DS_MAX_F32_gfx9
17164 { 1102, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1102 = DS_MAX_I32
17165 { 1103, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1103 = DS_MAX_I32_gfx9
17186 { 1124, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1124 = DS_MAX_U32
17187 { 1125, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1125 = DS_MAX_U32_gfx9
17190 { 1128, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1128 = DS_MIN_F32
17191 { 1129, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1129 = DS_MIN_F32_gfx9
17194 { 1132, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1132 = DS_MIN_I32
17195 { 1133, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1133 = DS_MIN_I32_gfx9
17216 { 1154, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1154 = DS_MIN_U32
17217 { 1155, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1155 = DS_MIN_U32_gfx9
17230 { 1168, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1168 = DS_OR_B32
17231 { 1169, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1169 = DS_OR_B32_gfx9
17252 { 1190, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1190 = DS_READ_B32
17253 { 1191, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1191 = DS_READ_B32_gfx9
17258 { 1196, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1196 = DS_READ_I16
17259 { 1197, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1197 = DS_READ_I16_gfx9
17260 { 1198, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1198 = DS_READ_I8
17263 { 1201, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1201 = DS_READ_I8_gfx9
17264 { 1202, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1202 = DS_READ_U16
17267 { 1205, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1205 = DS_READ_U16_gfx9
17268 { 1206, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1206 = DS_READ_U8
17271 { 1209, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1209 = DS_READ_U8_gfx9
17278 { 1216, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1216 = DS_RSUB_U32
17279 { 1217, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1217 = DS_RSUB_U32_gfx9
17288 { 1226, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1226 = DS_SUB_U32
17289 { 1227, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1227 = DS_SUB_U32_gfx9
17292 { 1230, 4, 1, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1230 = DS_SWIZZLE_B32
17306 { 1244, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1244 = DS_WRITE_B16
17307 { 1245, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1245 = DS_WRITE_B16_D16_HI
17308 { 1246, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1246 = DS_WRITE_B16_gfx9
17309 { 1247, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1247 = DS_WRITE_B32
17310 { 1248, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1248 = DS_WRITE_B32_gfx9
17313 { 1251, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1251 = DS_WRITE_B8
17314 { 1252, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1252 = DS_WRITE_B8_D16_HI
17315 { 1253, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1253 = DS_WRITE_B8_gfx9
17332 { 1270, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1270 = DS_XOR_B32
17333 { 1271, 4, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x80400400000ULL, ImplicitList2, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1271 = DS_XOR_B32_gfx9
19720 { 3658, 4, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #3658 = V_INTERP_P1_F32
21530 { 5468, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5468 = DS_ADD_F32_gfx10
21531 { 5469, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5469 = DS_ADD_F32_vi
21548 { 5486, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5486 = DS_ADD_U32_gfx10
21549 { 5487, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5487 = DS_ADD_U32_gfx6_gfx7
21550 { 5488, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5488 = DS_ADD_U32_vi
21554 { 5492, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5492 = DS_AND_B32_gfx10
21555 { 5493, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5493 = DS_AND_B32_gfx6_gfx7
21556 { 5494, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5494 = DS_AND_B32_vi
21619 { 5557, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5557 = DS_DEC_U32_gfx10
21620 { 5558, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5558 = DS_DEC_U32_gfx6_gfx7
21621 { 5559, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5559 = DS_DEC_U32_vi
21655 { 5593, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5593 = DS_INC_U32_gfx10
21656 { 5594, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5594 = DS_INC_U32_gfx6_gfx7
21657 { 5595, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5595 = DS_INC_U32_vi
21661 { 5599, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5599 = DS_MAX_F32_gfx10
21662 { 5600, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5600 = DS_MAX_F32_gfx6_gfx7
21663 { 5601, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5601 = DS_MAX_F32_vi
21667 { 5605, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5605 = DS_MAX_I32_gfx10
21668 { 5606, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5606 = DS_MAX_I32_gfx6_gfx7
21669 { 5607, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5607 = DS_MAX_I32_vi
21709 { 5647, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5647 = DS_MAX_U32_gfx10
21710 { 5648, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5648 = DS_MAX_U32_gfx6_gfx7
21711 { 5649, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5649 = DS_MAX_U32_vi
21715 { 5653, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5653 = DS_MIN_F32_gfx10
21716 { 5654, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5654 = DS_MIN_F32_gfx6_gfx7
21717 { 5655, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5655 = DS_MIN_F32_vi
21721 { 5659, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5659 = DS_MIN_I32_gfx10
21722 { 5660, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5660 = DS_MIN_I32_gfx6_gfx7
21723 { 5661, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5661 = DS_MIN_I32_vi
21763 { 5701, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5701 = DS_MIN_U32_gfx10
21764 { 5702, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5702 = DS_MIN_U32_gfx6_gfx7
21765 { 5703, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5703 = DS_MIN_U32_vi
21787 { 5725, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5725 = DS_OR_B32_gfx10
21788 { 5726, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5726 = DS_OR_B32_gfx6_gfx7
21789 { 5727, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5727 = DS_OR_B32_vi
21824 { 5762, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5762 = DS_READ_B32_gfx10
21825 { 5763, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5763 = DS_READ_B32_gfx6_gfx7
21826 { 5764, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5764 = DS_READ_B32_vi
21833 { 5771, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5771 = DS_READ_I16_gfx10
21834 { 5772, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5772 = DS_READ_I16_gfx6_gfx7
21835 { 5773, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5773 = DS_READ_I16_vi
21840 { 5778, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5778 = DS_READ_I8_gfx10
21841 { 5779, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5779 = DS_READ_I8_gfx6_gfx7
21842 { 5780, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5780 = DS_READ_I8_vi
21847 { 5785, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5785 = DS_READ_U16_gfx10
21848 { 5786, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5786 = DS_READ_U16_gfx6_gfx7
21849 { 5787, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5787 = DS_READ_U16_vi
21854 { 5792, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5792 = DS_READ_U8_gfx10
21855 { 5793, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5793 = DS_READ_U8_gfx6_gfx7
21856 { 5794, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5794 = DS_READ_U8_vi
21869 { 5807, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5807 = DS_RSUB_U32_gfx10
21870 { 5808, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5808 = DS_RSUB_U32_gfx6_gfx7
21871 { 5809, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5809 = DS_RSUB_U32_vi
21887 { 5825, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5825 = DS_SUB_U32_gfx10
21888 { 5826, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5826 = DS_SUB_U32_gfx6_gfx7
21889 { 5827, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5827 = DS_SUB_U32_vi
21893 { 5831, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5831 = DS_SWIZZLE_B32_gfx10
21894 { 5832, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5832 = DS_SWIZZLE_B32_gfx6_gfx7
21895 { 5833, 4, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5833 = DS_SWIZZLE_B32_vi
21916 { 5854, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5854 = DS_WRITE_B16_D16_HI_gfx10
21917 { 5855, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5855 = DS_WRITE_B16_D16_HI_vi
21918 { 5856, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5856 = DS_WRITE_B16_gfx10
21919 { 5857, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5857 = DS_WRITE_B16_gfx6_gfx7
21920 { 5858, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5858 = DS_WRITE_B16_vi
21921 { 5859, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5859 = DS_WRITE_B32_gfx10
21922 { 5860, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5860 = DS_WRITE_B32_gfx6_gfx7
21923 { 5861, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5861 = DS_WRITE_B32_vi
21927 { 5865, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5865 = DS_WRITE_B8_D16_HI_gfx10
21928 { 5866, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5866 = DS_WRITE_B8_D16_HI_vi
21929 { 5867, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5867 = DS_WRITE_B8_gfx10
21930 { 5868, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5868 = DS_WRITE_B8_gfx6_gfx7
21931 { 5869, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5869 = DS_WRITE_B8_vi
21959 { 5897, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5897 = DS_XOR_B32_gfx10
21960 { 5898, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5898 = DS_XOR_B32_gfx6_gfx7
21961 { 5899, 4, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #5899 = DS_XOR_B32_vi
30312 { 14250, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #14250 = V_INTERP_P1_F32_gfx10
30313 { 14251, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #14251 = V_INTERP_P1_F32_si
30314 { 14252, 4, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #14252 = V_INTERP_P1_F32_vi