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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16082 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
16146 { 84, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #84 = G_FENCE
16236 { 174, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #174 = ADJCALLSTACKDOWN
16237 { 175, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000000001ULL, nullptr, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #175 = ADJCALLSTACKUP
16238 { 176, 2, 0, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x80000000001ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #176 = ATOMIC_FENCE
17147 { 1085, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1085 = DS_GWS_SEMA_P
17148 { 1086, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1086 = DS_GWS_SEMA_RELEASE_ALL
17149 { 1087, 2, 0, 8, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x80400400000ULL, ImplicitList4, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #1087 = DS_GWS_SEMA_V
18128 { 2066, 2, 0, 8, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x21ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #2066 = S_SETREG_IMM32_B32
21634 { 5572, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5572 = DS_GWS_SEMA_P_gfx10
21635 { 5573, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5573 = DS_GWS_SEMA_P_gfx6_gfx7
21636 { 5574, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5574 = DS_GWS_SEMA_P_vi
21637 { 5575, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5575 = DS_GWS_SEMA_RELEASE_ALL_gfx10
21638 { 5576, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5576 = DS_GWS_SEMA_RELEASE_ALL_gfx7
21639 { 5577, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5577 = DS_GWS_SEMA_RELEASE_ALL_vi
21640 { 5578, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5578 = DS_GWS_SEMA_V_gfx10
21641 { 5579, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5579 = DS_GWS_SEMA_V_gfx6_gfx7
21642 { 5580, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #5580 = DS_GWS_SEMA_V_vi
27681 { 11619, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #11619 = S_SETREG_IMM32_B32_gfx10
27682 { 11620, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #11620 = S_SETREG_IMM32_B32_gfx6_gfx7
27683 { 11621, 2, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #11621 = S_SETREG_IMM32_B32_vi