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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16772 { 710, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #710 = BUFFER_LOAD_SBYTE_D16_ADDR64
16773 { 711, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #711 = BUFFER_LOAD_SBYTE_D16_BOTHEN
16774 { 712, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #712 = BUFFER_LOAD_SBYTE_D16_BOTHEN_exact
16775 { 713, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #713 = BUFFER_LOAD_SBYTE_D16_HI_ADDR64
16776 { 714, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #714 = BUFFER_LOAD_SBYTE_D16_HI_BOTHEN
16777 { 715, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #715 = BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_exact
16805 { 743, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #743 = BUFFER_LOAD_SHORT_D16_ADDR64
16806 { 744, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #744 = BUFFER_LOAD_SHORT_D16_BOTHEN
16807 { 745, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #745 = BUFFER_LOAD_SHORT_D16_BOTHEN_exact
16808 { 746, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #746 = BUFFER_LOAD_SHORT_D16_HI_ADDR64
16809 { 747, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #747 = BUFFER_LOAD_SHORT_D16_HI_BOTHEN
16810 { 748, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #748 = BUFFER_LOAD_SHORT_D16_HI_BOTHEN_exact
16844 { 782, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #782 = BUFFER_LOAD_UBYTE_D16_ADDR64
16845 { 783, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #783 = BUFFER_LOAD_UBYTE_D16_BOTHEN
16846 { 784, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #784 = BUFFER_LOAD_UBYTE_D16_BOTHEN_exact
16847 { 785, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #785 = BUFFER_LOAD_UBYTE_D16_HI_ADDR64
16848 { 786, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #786 = BUFFER_LOAD_UBYTE_D16_HI_BOTHEN
16849 { 787, 11, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #787 = BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_exact
21178 { 5116, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5116 = BUFFER_LOAD_SBYTE_D16_BOTHEN_gfx10
21179 { 5117, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5117 = BUFFER_LOAD_SBYTE_D16_BOTHEN_vi
21180 { 5118, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5118 = BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_gfx10
21181 { 5119, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5119 = BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi
21216 { 5154, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5154 = BUFFER_LOAD_SHORT_D16_BOTHEN_gfx10
21217 { 5155, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5155 = BUFFER_LOAD_SHORT_D16_BOTHEN_vi
21218 { 5156, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5156 = BUFFER_LOAD_SHORT_D16_HI_BOTHEN_gfx10
21219 { 5157, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5157 = BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi
21262 { 5200, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5200 = BUFFER_LOAD_UBYTE_D16_BOTHEN_gfx10
21263 { 5201, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5201 = BUFFER_LOAD_UBYTE_D16_BOTHEN_vi
21264 { 5202, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5202 = BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_gfx10
21265 { 5203, 11, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80300010000ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #5203 = BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi