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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc28115 { 12053, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #12053 = V_CEIL_F16_dpp_gfx10
28125 { 12063, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #12063 = V_CEIL_F32_dpp_gfx10
29723 { 13661, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13661 = V_COS_F16_dpp_gfx10
29733 { 13671, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13671 = V_COS_F32_dpp_gfx10
29757 { 13695, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13695 = V_CVT_F16_F32_dpp_gfx10
29789 { 13727, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13727 = V_CVT_F32_F16_dpp_gfx10
29897 { 13835, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13835 = V_CVT_FLR_I32_F32_dpp_gfx10
29909 { 13847, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13847 = V_CVT_I16_F16_dpp_gfx10
29919 { 13857, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13857 = V_CVT_I32_F32_dpp_gfx10
29937 { 13875, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13875 = V_CVT_NORM_I16_F16_dpp_gfx10
29947 { 13885, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13885 = V_CVT_NORM_U16_F16_dpp_gfx10
30000 { 13938, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13938 = V_CVT_RPI_I32_F32_dpp_gfx10
30012 { 13950, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13950 = V_CVT_U16_F16_dpp_gfx10
30022 { 13960, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #13960 = V_CVT_U32_F32_dpp_gfx10
30090 { 14028, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14028 = V_EXP_F16_dpp_gfx10
30100 { 14038, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14038 = V_EXP_F32_dpp_gfx10
30155 { 14093, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14093 = V_FLOOR_F16_dpp_gfx10
30165 { 14103, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14103 = V_FLOOR_F32_dpp_gfx10
30215 { 14153, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14153 = V_FRACT_F16_dpp_gfx10
30225 { 14163, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14163 = V_FRACT_F32_dpp_gfx10
30243 { 14181, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14181 = V_FREXP_EXP_I16_F16_dpp_gfx10
30253 { 14191, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14191 = V_FREXP_EXP_I32_F32_dpp_gfx10
30271 { 14209, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14209 = V_FREXP_MANT_F16_dpp_gfx10
30281 { 14219, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14219 = V_FREXP_MANT_F32_dpp_gfx10
30347 { 14285, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14285 = V_LOG_F16_dpp_gfx10
30357 { 14295, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14295 = V_LOG_F32_dpp_gfx10
30939 { 14877, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14877 = V_RCP_F16_dpp_gfx10
30949 { 14887, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14887 = V_RCP_F32_dpp_gfx10
30967 { 14905, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14905 = V_RCP_IFLAG_F32_dpp_gfx10
30985 { 14923, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14923 = V_RNDNE_F16_dpp_gfx10
30995 { 14933, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14933 = V_RNDNE_F32_dpp_gfx10
31017 { 14955, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14955 = V_RSQ_F16_dpp_gfx10
31027 { 14965, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #14965 = V_RSQ_F32_dpp_gfx10
31073 { 15011, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #15011 = V_SIN_F16_dpp_gfx10
31083 { 15021, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #15021 = V_SIN_F32_dpp_gfx10
31095 { 15033, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #15033 = V_SQRT_F16_dpp_gfx10
31105 { 15043, 9, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #15043 = V_SQRT_F32_dpp_gfx10
31270 { 15208, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #15208 = V_TRUNC_F16_dpp_gfx10
31280 { 15218, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo713, -1 ,nullptr }, // Inst #15218 = V_TRUNC_F32_dpp_gfx10