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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc28103 { 12041, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #12041 = V_BFREV_B32_dpp_gfx10
29769 { 13707, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13707 = V_CVT_F16_I16_dpp_gfx10
29779 { 13717, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13717 = V_CVT_F16_U16_dpp_gfx10
29807 { 13745, 8, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13745 = V_CVT_F32_I32_dpp_gfx10
29819 { 13757, 8, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13757 = V_CVT_F32_U32_dpp_gfx10
29831 { 13769, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13769 = V_CVT_F32_UBYTE0_dpp_gfx10
29843 { 13781, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13781 = V_CVT_F32_UBYTE1_dpp_gfx10
29855 { 13793, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13793 = V_CVT_F32_UBYTE2_dpp_gfx10
29867 { 13805, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13805 = V_CVT_F32_UBYTE3_dpp_gfx10
29957 { 13895, 8, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #13895 = V_CVT_OFF_F32_I4_dpp_gfx10
30119 { 14057, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #14057 = V_FFBH_I32_dpp_gfx10
30131 { 14069, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #14069 = V_FFBH_U32_dpp_gfx10
30143 { 14081, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #14081 = V_FFBL_B32_dpp_gfx10
30710 { 14648, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #14648 = V_MOV_B32_dpp_gfx10
30722 { 14660, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #14660 = V_MOV_FED_B32_dpp_gfx10
30857 { 14795, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #14795 = V_NOT_B32_dpp_gfx10
31059 { 14997, 8, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo712, -1 ,nullptr }, // Inst #14997 = V_SAT_PK_U8_I16_dpp_gfx10