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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc27991 { 11929, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #11929 = V_ADD_F16_dpp_gfx10
28001 { 11939, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #11939 = V_ADD_F32_dpp_gfx10
29707 { 13645, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #13645 = V_CNDMASK_B32_dpp_gfx10
29709 { 13647, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #13647 = V_CNDMASK_B32_dpp_w32_gfx10
29710 { 13648, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #13648 = V_CNDMASK_B32_dpp_w64_gfx10
30325 { 14263, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14263 = V_LDEXP_F16_dpp_gfx10
30440 { 14378, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14378 = V_MAC_LEGACY_F32_dpp_gfx10
30506 { 14444, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14444 = V_MAX_F16_dpp_gfx10
30516 { 14454, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14454 = V_MAX_F32_dpp_gfx10
30627 { 14565, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14565 = V_MIN_F16_dpp_gfx10
30637 { 14575, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14575 = V_MIN_F32_dpp_gfx10
30745 { 14683, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14683 = V_MUL_F16_dpp_gfx10
30755 { 14693, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14693 = V_MUL_F32_dpp_gfx10
30812 { 14750, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #14750 = V_MUL_LEGACY_F32_dpp_gfx10
31159 { 15097, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #15097 = V_SUBREV_F16_dpp_gfx10
31169 { 15107, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #15107 = V_SUBREV_F32_dpp_gfx10
31217 { 15155, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #15155 = V_SUB_F16_dpp_gfx10
31227 { 15165, 11, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo711, -1 ,nullptr }, // Inst #15165 = V_SUB_F32_dpp_gfx10