|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc27977 { 11915, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #11915 = V_ADD_CO_CI_U32_dpp_gfx10
27978 { 11916, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #11916 = V_ADD_CO_CI_U32_dpp_w32_gfx10
27979 { 11917, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #11917 = V_ADD_CO_CI_U32_dpp_w64_gfx10
28025 { 11963, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #11963 = V_ADD_NC_U32_dpp_gfx10
28049 { 11987, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #11987 = V_AND_B32_dpp_gfx10
28069 { 12007, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #12007 = V_ASHRREV_I32_dpp_gfx10
30382 { 14320, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14320 = V_LSHLREV_B32_dpp_gfx10
30409 { 14347, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14347 = V_LSHRREV_B32_dpp_gfx10
30537 { 14475, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14475 = V_MAX_I32_dpp_gfx10
30557 { 14495, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14495 = V_MAX_U32_dpp_gfx10
30658 { 14596, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14596 = V_MIN_I32_dpp_gfx10
30678 { 14616, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14616 = V_MIN_U32_dpp_gfx10
30770 { 14708, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14708 = V_MUL_HI_I32_I24_dpp_gfx10
30785 { 14723, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14723 = V_MUL_HI_U32_U24_dpp_gfx10
30800 { 14738, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14738 = V_MUL_I32_I24_dpp_gfx10
30836 { 14774, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14774 = V_MUL_U32_U24_dpp_gfx10
30871 { 14809, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #14809 = V_OR_B32_dpp_gfx10
31145 { 15083, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #15083 = V_SUBREV_CO_CI_U32_dpp_gfx10
31146 { 15084, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #15084 = V_SUBREV_CO_CI_U32_dpp_w32_gfx10
31147 { 15085, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #15085 = V_SUBREV_CO_CI_U32_dpp_w64_gfx10
31183 { 15121, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #15121 = V_SUBREV_NC_U32_dpp_gfx10
31203 { 15141, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #15141 = V_SUB_CO_CI_U32_dpp_gfx10
31204 { 15142, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #15142 = V_SUB_CO_CI_U32_dpp_w32_gfx10
31205 { 15143, 9, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo710, -1 ,nullptr }, // Inst #15143 = V_SUB_CO_CI_U32_dpp_w64_gfx10
31246 { 15184, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #15184 = V_SUB_NC_U32_dpp_gfx10
31303 { 15241, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #15241 = V_XNOR_B32_dpp_gfx10
31314 { 15252, 9, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo710, -1 ,nullptr }, // Inst #15252 = V_XOR_B32_dpp_gfx10