|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc27974 { 11912, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #11912 = V_ADD_CO_CI_U32_dpp8_gfx10
27975 { 11913, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #11913 = V_ADD_CO_CI_U32_dpp8_w32_gfx10
27976 { 11914, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #11914 = V_ADD_CO_CI_U32_dpp8_w64_gfx10
27990 { 11928, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #11928 = V_ADD_F16_dpp8_gfx10
28000 { 11938, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #11938 = V_ADD_F32_dpp8_gfx10
28024 { 11962, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #11962 = V_ADD_NC_U32_dpp8_gfx10
28048 { 11986, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #11986 = V_AND_B32_dpp8_gfx10
28068 { 12006, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #12006 = V_ASHRREV_I32_dpp8_gfx10
29704 { 13642, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #13642 = V_CNDMASK_B32_dpp8_gfx10
29705 { 13643, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #13643 = V_CNDMASK_B32_dpp8_w32_gfx10
29706 { 13644, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #13644 = V_CNDMASK_B32_dpp8_w64_gfx10
30324 { 14262, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14262 = V_LDEXP_F16_dpp8_gfx10
30381 { 14319, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14319 = V_LSHLREV_B32_dpp8_gfx10
30408 { 14346, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14346 = V_LSHRREV_B32_dpp8_gfx10
30439 { 14377, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14377 = V_MAC_LEGACY_F32_dpp8_gfx10
30505 { 14443, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14443 = V_MAX_F16_dpp8_gfx10
30515 { 14453, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14453 = V_MAX_F32_dpp8_gfx10
30536 { 14474, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14474 = V_MAX_I32_dpp8_gfx10
30556 { 14494, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14494 = V_MAX_U32_dpp8_gfx10
30626 { 14564, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14564 = V_MIN_F16_dpp8_gfx10
30636 { 14574, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14574 = V_MIN_F32_dpp8_gfx10
30657 { 14595, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14595 = V_MIN_I32_dpp8_gfx10
30677 { 14615, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14615 = V_MIN_U32_dpp8_gfx10
30744 { 14682, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14682 = V_MUL_F16_dpp8_gfx10
30754 { 14692, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14692 = V_MUL_F32_dpp8_gfx10
30769 { 14707, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14707 = V_MUL_HI_I32_I24_dpp8_gfx10
30784 { 14722, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14722 = V_MUL_HI_U32_U24_dpp8_gfx10
30799 { 14737, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14737 = V_MUL_I32_I24_dpp8_gfx10
30811 { 14749, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14749 = V_MUL_LEGACY_F32_dpp8_gfx10
30835 { 14773, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14773 = V_MUL_U32_U24_dpp8_gfx10
30870 { 14808, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #14808 = V_OR_B32_dpp8_gfx10
31142 { 15080, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #15080 = V_SUBREV_CO_CI_U32_dpp8_gfx10
31143 { 15081, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #15081 = V_SUBREV_CO_CI_U32_dpp8_w32_gfx10
31144 { 15082, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #15082 = V_SUBREV_CO_CI_U32_dpp8_w64_gfx10
31158 { 15096, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15096 = V_SUBREV_F16_dpp8_gfx10
31168 { 15106, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15106 = V_SUBREV_F32_dpp8_gfx10
31182 { 15120, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15120 = V_SUBREV_NC_U32_dpp8_gfx10
31200 { 15138, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #15138 = V_SUB_CO_CI_U32_dpp8_gfx10
31201 { 15139, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #15139 = V_SUB_CO_CI_U32_dpp8_w32_gfx10
31202 { 15140, 6, 1, 8, 9, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList13, ImplicitList14, OperandInfo709, -1 ,nullptr }, // Inst #15140 = V_SUB_CO_CI_U32_dpp8_w64_gfx10
31216 { 15154, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15154 = V_SUB_F16_dpp8_gfx10
31226 { 15164, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15164 = V_SUB_F32_dpp8_gfx10
31245 { 15183, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15183 = V_SUB_NC_U32_dpp8_gfx10
31302 { 15240, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15240 = V_XNOR_B32_dpp8_gfx10
31313 { 15251, 6, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo709, -1 ,nullptr }, // Inst #15251 = V_XOR_B32_dpp8_gfx10