|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16255 { 193, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #193 = BUFFER_ATOMIC_ADD_X2_ADDR64_RTN
16257 { 195, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #195 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN
16275 { 213, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #213 = BUFFER_ATOMIC_AND_X2_ADDR64_RTN
16277 { 215, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #215 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN
16285 { 223, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #223 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN
16287 { 225, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #225 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN
16315 { 253, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #253 = BUFFER_ATOMIC_DEC_X2_ADDR64_RTN
16317 { 255, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #255 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN
16325 { 263, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #263 = BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN
16327 { 265, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #265 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN
16355 { 293, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #293 = BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN
16357 { 295, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #295 = BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN
16375 { 313, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #313 = BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN
16377 { 315, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #315 = BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN
16395 { 333, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #333 = BUFFER_ATOMIC_INC_X2_ADDR64_RTN
16397 { 335, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #335 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN
16415 { 353, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #353 = BUFFER_ATOMIC_OR_X2_ADDR64_RTN
16417 { 355, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #355 = BUFFER_ATOMIC_OR_X2_BOTHEN_RTN
16440 { 378, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #378 = BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN
16442 { 380, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #380 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN
16460 { 398, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #398 = BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN
16462 { 400, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #400 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN
16480 { 418, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #418 = BUFFER_ATOMIC_SUB_X2_ADDR64_RTN
16482 { 420, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #420 = BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN
16500 { 438, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #438 = BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN
16502 { 440, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #440 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN
16520 { 458, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #458 = BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN
16522 { 460, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #460 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN
16540 { 478, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #478 = BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN
16542 { 480, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #480 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN
16560 { 498, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #498 = BUFFER_ATOMIC_XOR_X2_ADDR64_RTN
16562 { 500, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #500 = BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN
20216 { 4154, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4154 = BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_gfx6_gfx7
20218 { 4156, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4156 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx10
20219 { 4157, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4157 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_gfx6_gfx7
20220 { 4158, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4158 = BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi
20268 { 4206, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4206 = BUFFER_ATOMIC_AND_X2_ADDR64_RTN_gfx6_gfx7
20270 { 4208, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4208 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx10
20271 { 4209, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4209 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_gfx6_gfx7
20272 { 4210, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4210 = BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi
20294 { 4232, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4232 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_gfx6_gfx7
20296 { 4234, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4234 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx10
20297 { 4235, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4235 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_gfx6_gfx7
20298 { 4236, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4236 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi
20372 { 4310, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4310 = BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_gfx6_gfx7
20374 { 4312, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4312 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx10
20375 { 4313, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4313 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_gfx6_gfx7
20376 { 4314, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4314 = BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi
20398 { 4336, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4336 = BUFFER_ATOMIC_FCMPSWAP_ADDR64_RTN_gfx6_gfx7
20400 { 4338, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4338 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx10
20401 { 4339, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4339 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN_RTN_gfx6_gfx7
20452 { 4390, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4390 = BUFFER_ATOMIC_FMAX_X2_ADDR64_RTN_gfx6_gfx7
20454 { 4392, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4392 = BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx10
20455 { 4393, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4393 = BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN_gfx6_gfx7
20488 { 4426, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4426 = BUFFER_ATOMIC_FMIN_X2_ADDR64_RTN_gfx6_gfx7
20490 { 4428, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4428 = BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx10
20491 { 4429, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4429 = BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN_gfx6_gfx7
20532 { 4470, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4470 = BUFFER_ATOMIC_INC_X2_ADDR64_RTN_gfx6_gfx7
20534 { 4472, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4472 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx10
20535 { 4473, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4473 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_gfx6_gfx7
20536 { 4474, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4474 = BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi
20584 { 4522, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4522 = BUFFER_ATOMIC_OR_X2_ADDR64_RTN_gfx6_gfx7
20586 { 4524, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4524 = BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx10
20587 { 4525, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4525 = BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_gfx6_gfx7
20588 { 4526, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4526 = BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi
20640 { 4578, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4578 = BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_gfx6_gfx7
20642 { 4580, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4580 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx10
20643 { 4581, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4581 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_gfx6_gfx7
20644 { 4582, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4582 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi
20692 { 4630, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4630 = BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_gfx6_gfx7
20694 { 4632, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4632 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx10
20695 { 4633, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4633 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_gfx6_gfx7
20696 { 4634, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4634 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi
20744 { 4682, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4682 = BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_gfx6_gfx7
20746 { 4684, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4684 = BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx10
20747 { 4685, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4685 = BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_gfx6_gfx7
20748 { 4686, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4686 = BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi
20796 { 4734, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4734 = BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_gfx6_gfx7
20798 { 4736, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4736 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx10
20799 { 4737, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4737 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_gfx6_gfx7
20800 { 4738, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4738 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi
20848 { 4786, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4786 = BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_gfx6_gfx7
20850 { 4788, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4788 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx10
20851 { 4789, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4789 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_gfx6_gfx7
20852 { 4790, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4790 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi
20900 { 4838, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4838 = BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_gfx6_gfx7
20902 { 4840, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4840 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx10
20903 { 4841, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4841 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_gfx6_gfx7
20904 { 4842, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4842 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi
20952 { 4890, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4890 = BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_gfx6_gfx7
20954 { 4892, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4892 = BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx10
20955 { 4893, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4893 = BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_gfx6_gfx7
20956 { 4894, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4894 = BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi