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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19999 { 3937, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3937 = V_PK_ADD_I16
20000 { 3938, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3938 = V_PK_ADD_U16
20001 { 3939, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3939 = V_PK_ASHRREV_I16
20007 { 3945, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3945 = V_PK_LSHLREV_B16
20008 { 3946, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3946 = V_PK_LSHRREV_B16
20012 { 3950, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3950 = V_PK_MAX_I16
20013 { 3951, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3951 = V_PK_MAX_U16
20015 { 3953, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3953 = V_PK_MIN_I16
20016 { 3954, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3954 = V_PK_MIN_U16
20018 { 3956, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3956 = V_PK_MUL_LO_U16
20019 { 3957, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3957 = V_PK_SUB_I16
20020 { 3958, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #3958 = V_PK_SUB_U16
30893 { 14831, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14831 = V_PK_ADD_I16_gfx10
30894 { 14832, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14832 = V_PK_ADD_I16_vi
30895 { 14833, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14833 = V_PK_ADD_U16_gfx10
30896 { 14834, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14834 = V_PK_ADD_U16_vi
30897 { 14835, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14835 = V_PK_ASHRREV_I16_gfx10
30898 { 14836, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14836 = V_PK_ASHRREV_I16_vi
30903 { 14841, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14841 = V_PK_LSHLREV_B16_gfx10
30904 { 14842, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14842 = V_PK_LSHLREV_B16_vi
30905 { 14843, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14843 = V_PK_LSHRREV_B16_gfx10
30906 { 14844, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14844 = V_PK_LSHRREV_B16_vi
30913 { 14851, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14851 = V_PK_MAX_I16_gfx10
30914 { 14852, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14852 = V_PK_MAX_I16_vi
30915 { 14853, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14853 = V_PK_MAX_U16_gfx10
30916 { 14854, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14854 = V_PK_MAX_U16_vi
30919 { 14857, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14857 = V_PK_MIN_I16_gfx10
30920 { 14858, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14858 = V_PK_MIN_I16_vi
30921 { 14859, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14859 = V_PK_MIN_U16_gfx10
30922 { 14860, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14860 = V_PK_MIN_U16_vi
30925 { 14863, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14863 = V_PK_MUL_LO_U16_gfx10
30926 { 14864, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14864 = V_PK_MUL_LO_U16_vi
30927 { 14865, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14865 = V_PK_SUB_I16_gfx10
30928 { 14866, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14866 = V_PK_SUB_I16_vi
30929 { 14867, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14867 = V_PK_SUB_U16_gfx10
30930 { 14868, 10, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3c00000001402ULL, ImplicitList2, nullptr, OperandInfo423, -1 ,nullptr }, // Inst #14868 = V_PK_SUB_U16_vi