|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16254 { 192, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #192 = BUFFER_ATOMIC_ADD_X2_ADDR64
16256 { 194, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #194 = BUFFER_ATOMIC_ADD_X2_BOTHEN
16274 { 212, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #212 = BUFFER_ATOMIC_AND_X2_ADDR64
16276 { 214, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #214 = BUFFER_ATOMIC_AND_X2_BOTHEN
16284 { 222, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #222 = BUFFER_ATOMIC_CMPSWAP_ADDR64
16286 { 224, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #224 = BUFFER_ATOMIC_CMPSWAP_BOTHEN
16314 { 252, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #252 = BUFFER_ATOMIC_DEC_X2_ADDR64
16316 { 254, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #254 = BUFFER_ATOMIC_DEC_X2_BOTHEN
16324 { 262, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #262 = BUFFER_ATOMIC_FCMPSWAP_ADDR64
16326 { 264, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #264 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN
16354 { 292, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #292 = BUFFER_ATOMIC_FMAX_X2_ADDR64
16356 { 294, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #294 = BUFFER_ATOMIC_FMAX_X2_BOTHEN
16374 { 312, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #312 = BUFFER_ATOMIC_FMIN_X2_ADDR64
16376 { 314, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #314 = BUFFER_ATOMIC_FMIN_X2_BOTHEN
16394 { 332, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #332 = BUFFER_ATOMIC_INC_X2_ADDR64
16396 { 334, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #334 = BUFFER_ATOMIC_INC_X2_BOTHEN
16414 { 352, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #352 = BUFFER_ATOMIC_OR_X2_ADDR64
16416 { 354, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #354 = BUFFER_ATOMIC_OR_X2_BOTHEN
16439 { 377, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #377 = BUFFER_ATOMIC_SMAX_X2_ADDR64
16441 { 379, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #379 = BUFFER_ATOMIC_SMAX_X2_BOTHEN
16459 { 397, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #397 = BUFFER_ATOMIC_SMIN_X2_ADDR64
16461 { 399, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #399 = BUFFER_ATOMIC_SMIN_X2_BOTHEN
16479 { 417, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #417 = BUFFER_ATOMIC_SUB_X2_ADDR64
16481 { 419, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #419 = BUFFER_ATOMIC_SUB_X2_BOTHEN
16499 { 437, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #437 = BUFFER_ATOMIC_SWAP_X2_ADDR64
16501 { 439, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #439 = BUFFER_ATOMIC_SWAP_X2_BOTHEN
16519 { 457, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #457 = BUFFER_ATOMIC_UMAX_X2_ADDR64
16521 { 459, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #459 = BUFFER_ATOMIC_UMAX_X2_BOTHEN
16539 { 477, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #477 = BUFFER_ATOMIC_UMIN_X2_ADDR64
16541 { 479, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #479 = BUFFER_ATOMIC_UMIN_X2_BOTHEN
16559 { 497, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #497 = BUFFER_ATOMIC_XOR_X2_ADDR64
16561 { 499, 6, 0, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #499 = BUFFER_ATOMIC_XOR_X2_BOTHEN
20217 { 4155, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4155 = BUFFER_ATOMIC_ADD_X2_ADDR64_gfx6_gfx7
20221 { 4159, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4159 = BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx10
20222 { 4160, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4160 = BUFFER_ATOMIC_ADD_X2_BOTHEN_gfx6_gfx7
20223 { 4161, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4161 = BUFFER_ATOMIC_ADD_X2_BOTHEN_vi
20269 { 4207, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4207 = BUFFER_ATOMIC_AND_X2_ADDR64_gfx6_gfx7
20273 { 4211, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4211 = BUFFER_ATOMIC_AND_X2_BOTHEN_gfx10
20274 { 4212, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4212 = BUFFER_ATOMIC_AND_X2_BOTHEN_gfx6_gfx7
20275 { 4213, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4213 = BUFFER_ATOMIC_AND_X2_BOTHEN_vi
20295 { 4233, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4233 = BUFFER_ATOMIC_CMPSWAP_ADDR64_gfx6_gfx7
20299 { 4237, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4237 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx10
20300 { 4238, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4238 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_gfx6_gfx7
20301 { 4239, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4239 = BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi
20373 { 4311, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4311 = BUFFER_ATOMIC_DEC_X2_ADDR64_gfx6_gfx7
20377 { 4315, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4315 = BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx10
20378 { 4316, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4316 = BUFFER_ATOMIC_DEC_X2_BOTHEN_gfx6_gfx7
20379 { 4317, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4317 = BUFFER_ATOMIC_DEC_X2_BOTHEN_vi
20399 { 4337, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4337 = BUFFER_ATOMIC_FCMPSWAP_ADDR64_gfx6_gfx7
20402 { 4340, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4340 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx10
20403 { 4341, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4341 = BUFFER_ATOMIC_FCMPSWAP_BOTHEN_gfx6_gfx7
20453 { 4391, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4391 = BUFFER_ATOMIC_FMAX_X2_ADDR64_gfx6_gfx7
20456 { 4394, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4394 = BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx10
20457 { 4395, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4395 = BUFFER_ATOMIC_FMAX_X2_BOTHEN_gfx6_gfx7
20489 { 4427, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4427 = BUFFER_ATOMIC_FMIN_X2_ADDR64_gfx6_gfx7
20492 { 4430, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4430 = BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx10
20493 { 4431, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4431 = BUFFER_ATOMIC_FMIN_X2_BOTHEN_gfx6_gfx7
20533 { 4471, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4471 = BUFFER_ATOMIC_INC_X2_ADDR64_gfx6_gfx7
20537 { 4475, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4475 = BUFFER_ATOMIC_INC_X2_BOTHEN_gfx10
20538 { 4476, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4476 = BUFFER_ATOMIC_INC_X2_BOTHEN_gfx6_gfx7
20539 { 4477, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4477 = BUFFER_ATOMIC_INC_X2_BOTHEN_vi
20585 { 4523, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4523 = BUFFER_ATOMIC_OR_X2_ADDR64_gfx6_gfx7
20589 { 4527, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4527 = BUFFER_ATOMIC_OR_X2_BOTHEN_gfx10
20590 { 4528, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4528 = BUFFER_ATOMIC_OR_X2_BOTHEN_gfx6_gfx7
20591 { 4529, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4529 = BUFFER_ATOMIC_OR_X2_BOTHEN_vi
20641 { 4579, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4579 = BUFFER_ATOMIC_SMAX_X2_ADDR64_gfx6_gfx7
20645 { 4583, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4583 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx10
20646 { 4584, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4584 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_gfx6_gfx7
20647 { 4585, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4585 = BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi
20693 { 4631, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4631 = BUFFER_ATOMIC_SMIN_X2_ADDR64_gfx6_gfx7
20697 { 4635, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4635 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx10
20698 { 4636, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4636 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_gfx6_gfx7
20699 { 4637, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4637 = BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi
20745 { 4683, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4683 = BUFFER_ATOMIC_SUB_X2_ADDR64_gfx6_gfx7
20749 { 4687, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4687 = BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx10
20750 { 4688, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4688 = BUFFER_ATOMIC_SUB_X2_BOTHEN_gfx6_gfx7
20751 { 4689, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4689 = BUFFER_ATOMIC_SUB_X2_BOTHEN_vi
20797 { 4735, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4735 = BUFFER_ATOMIC_SWAP_X2_ADDR64_gfx6_gfx7
20801 { 4739, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4739 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx10
20802 { 4740, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4740 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_gfx6_gfx7
20803 { 4741, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4741 = BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi
20849 { 4787, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4787 = BUFFER_ATOMIC_UMAX_X2_ADDR64_gfx6_gfx7
20853 { 4791, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4791 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx10
20854 { 4792, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4792 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_gfx6_gfx7
20855 { 4793, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4793 = BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi
20901 { 4839, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4839 = BUFFER_ATOMIC_UMIN_X2_ADDR64_gfx6_gfx7
20905 { 4843, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4843 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx10
20906 { 4844, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4844 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_gfx6_gfx7
20907 { 4845, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4845 = BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi
20953 { 4891, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4891 = BUFFER_ATOMIC_XOR_X2_ADDR64_gfx6_gfx7
20957 { 4895, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4895 = BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx10
20958 { 4896, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4896 = BUFFER_ATOMIC_XOR_X2_BOTHEN_gfx6_gfx7
20959 { 4897, 6, 0, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4897 = BUFFER_ATOMIC_XOR_X2_BOTHEN_vi