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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16253 { 191, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #191 = BUFFER_ATOMIC_ADD_OFFSET_RTN
16273 { 211, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #211 = BUFFER_ATOMIC_AND_OFFSET_RTN
16313 { 251, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #251 = BUFFER_ATOMIC_DEC_OFFSET_RTN
16353 { 291, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #291 = BUFFER_ATOMIC_FMAX_OFFSET_RTN
16373 { 311, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #311 = BUFFER_ATOMIC_FMIN_OFFSET_RTN
16393 { 331, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #331 = BUFFER_ATOMIC_INC_OFFSET_RTN
16413 { 351, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #351 = BUFFER_ATOMIC_OR_OFFSET_RTN
16438 { 376, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #376 = BUFFER_ATOMIC_SMAX_OFFSET_RTN
16458 { 396, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #396 = BUFFER_ATOMIC_SMIN_OFFSET_RTN
16478 { 416, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #416 = BUFFER_ATOMIC_SUB_OFFSET_RTN
16498 { 436, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #436 = BUFFER_ATOMIC_SWAP_OFFSET_RTN
16518 { 456, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #456 = BUFFER_ATOMIC_UMAX_OFFSET_RTN
16538 { 476, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #476 = BUFFER_ATOMIC_UMIN_OFFSET_RTN
16558 { 496, 6, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #496 = BUFFER_ATOMIC_XOR_OFFSET_RTN
20210 { 4148, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4148 = BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx10
20211 { 4149, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4149 = BUFFER_ATOMIC_ADD_OFFSET_RTN_gfx6_gfx7
20212 { 4150, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4150 = BUFFER_ATOMIC_ADD_OFFSET_RTN_vi
20262 { 4200, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4200 = BUFFER_ATOMIC_AND_OFFSET_RTN_gfx10
20263 { 4201, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4201 = BUFFER_ATOMIC_AND_OFFSET_RTN_gfx6_gfx7
20264 { 4202, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4202 = BUFFER_ATOMIC_AND_OFFSET_RTN_vi
20366 { 4304, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4304 = BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx10
20367 { 4305, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4305 = BUFFER_ATOMIC_DEC_OFFSET_RTN_gfx6_gfx7
20368 { 4306, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4306 = BUFFER_ATOMIC_DEC_OFFSET_RTN_vi
20448 { 4386, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4386 = BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx10
20449 { 4387, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4387 = BUFFER_ATOMIC_FMAX_OFFSET_RTN_gfx6_gfx7
20484 { 4422, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4422 = BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx10
20485 { 4423, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4423 = BUFFER_ATOMIC_FMIN_OFFSET_RTN_gfx6_gfx7
20526 { 4464, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4464 = BUFFER_ATOMIC_INC_OFFSET_RTN_gfx10
20527 { 4465, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4465 = BUFFER_ATOMIC_INC_OFFSET_RTN_gfx6_gfx7
20528 { 4466, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4466 = BUFFER_ATOMIC_INC_OFFSET_RTN_vi
20578 { 4516, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4516 = BUFFER_ATOMIC_OR_OFFSET_RTN_gfx10
20579 { 4517, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4517 = BUFFER_ATOMIC_OR_OFFSET_RTN_gfx6_gfx7
20580 { 4518, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4518 = BUFFER_ATOMIC_OR_OFFSET_RTN_vi
20634 { 4572, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4572 = BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx10
20635 { 4573, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4573 = BUFFER_ATOMIC_SMAX_OFFSET_RTN_gfx6_gfx7
20636 { 4574, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4574 = BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi
20686 { 4624, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4624 = BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx10
20687 { 4625, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4625 = BUFFER_ATOMIC_SMIN_OFFSET_RTN_gfx6_gfx7
20688 { 4626, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4626 = BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi
20738 { 4676, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4676 = BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx10
20739 { 4677, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4677 = BUFFER_ATOMIC_SUB_OFFSET_RTN_gfx6_gfx7
20740 { 4678, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4678 = BUFFER_ATOMIC_SUB_OFFSET_RTN_vi
20790 { 4728, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4728 = BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx10
20791 { 4729, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4729 = BUFFER_ATOMIC_SWAP_OFFSET_RTN_gfx6_gfx7
20792 { 4730, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4730 = BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi
20842 { 4780, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4780 = BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx10
20843 { 4781, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4781 = BUFFER_ATOMIC_UMAX_OFFSET_RTN_gfx6_gfx7
20844 { 4782, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4782 = BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi
20894 { 4832, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4832 = BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx10
20895 { 4833, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4833 = BUFFER_ATOMIC_UMIN_OFFSET_RTN_gfx6_gfx7
20896 { 4834, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4834 = BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi
20946 { 4884, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4884 = BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx10
20947 { 4885, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4885 = BUFFER_ATOMIC_XOR_OFFSET_RTN_gfx6_gfx7
20948 { 4886, 6, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #4886 = BUFFER_ATOMIC_XOR_OFFSET_RTN_vi