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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19861 { 3799, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3799 = V_MFMA_F32_16X16X2BF16
19868 { 3806, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3806 = V_MFMA_F32_32X32X4BF16
19875 { 3813, 7, 1, 8, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3813 = V_MFMA_I32_16X16X4I8
19877 { 3815, 7, 1, 8, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #3815 = V_MFMA_I32_32X32X8I8
30593 { 14531, 7, 1, 8, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #14531 = V_MFMA_F32_16X16X2BF16_vi
30600 { 14538, 7, 1, 8, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x42000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #14538 = V_MFMA_F32_32X32X4BF16_vi
30607 { 14545, 7, 1, 8, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #14545 = V_MFMA_I32_16X16X4I8_vi
30609 { 14547, 7, 1, 8, 24, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo404, -1 ,nullptr }, // Inst #14547 = V_MFMA_I32_32X32X8I8_vi