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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19803 { 3741, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #3741 = V_MAD_I32_I24
19812 { 3750, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #3750 = V_MAD_U32_U24
19940 { 3878, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #3878 = V_MSAD_U8
20077 { 4015, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4015 = V_SAD_HI_U8
20078 { 4016, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4016 = V_SAD_U16
20079 { 4017, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4017 = V_SAD_U32
20080 { 4018, 5, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #4018 = V_SAD_U8
30464 { 14402, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14402 = V_MAD_I32_I24_gfx10
30465 { 14403, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14403 = V_MAD_I32_I24_gfx6_gfx7
30466 { 14404, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14404 = V_MAD_I32_I24_vi
30484 { 14422, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14422 = V_MAD_U32_U24_gfx10
30485 { 14423, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14423 = V_MAD_U32_U24_gfx6_gfx7
30486 { 14424, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14424 = V_MAD_U32_U24_vi
30739 { 14677, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14677 = V_MSAD_U8_gfx10
30740 { 14678, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14678 = V_MSAD_U8_gfx6_gfx7
30741 { 14679, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14679 = V_MSAD_U8_vi
31046 { 14984, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14984 = V_SAD_HI_U8_gfx10
31047 { 14985, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14985 = V_SAD_HI_U8_gfx6_gfx7
31048 { 14986, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14986 = V_SAD_HI_U8_vi
31049 { 14987, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14987 = V_SAD_U16_gfx10
31050 { 14988, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14988 = V_SAD_U16_gfx6_gfx7
31051 { 14989, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14989 = V_SAD_U16_vi
31052 { 14990, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14990 = V_SAD_U32_gfx10
31053 { 14991, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14991 = V_SAD_U32_gfx6_gfx7
31054 { 14992, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14992 = V_SAD_U32_vi
31055 { 14993, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14993 = V_SAD_U8_gfx10
31056 { 14994, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14994 = V_SAD_U8_gfx6_gfx7
31057 { 14995, 5, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc00000000402ULL, ImplicitList2, nullptr, OperandInfo400, -1 ,nullptr }, // Inst #14995 = V_SAD_U8_vi