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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19725 { 3663, 5, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #3663 = V_INTERP_P2_F32
28102 { 12040, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #12040 = V_BFREV_B32_dpp8_gfx10
28114 { 12052, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #12052 = V_CEIL_F16_dpp8_gfx10
28124 { 12062, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #12062 = V_CEIL_F32_dpp8_gfx10
29722 { 13660, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13660 = V_COS_F16_dpp8_gfx10
29732 { 13670, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13670 = V_COS_F32_dpp8_gfx10
29756 { 13694, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13694 = V_CVT_F16_F32_dpp8_gfx10
29768 { 13706, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13706 = V_CVT_F16_I16_dpp8_gfx10
29778 { 13716, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13716 = V_CVT_F16_U16_dpp8_gfx10
29788 { 13726, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13726 = V_CVT_F32_F16_dpp8_gfx10
29806 { 13744, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13744 = V_CVT_F32_I32_dpp8_gfx10
29818 { 13756, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13756 = V_CVT_F32_U32_dpp8_gfx10
29830 { 13768, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13768 = V_CVT_F32_UBYTE0_dpp8_gfx10
29842 { 13780, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13780 = V_CVT_F32_UBYTE1_dpp8_gfx10
29854 { 13792, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13792 = V_CVT_F32_UBYTE2_dpp8_gfx10
29866 { 13804, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13804 = V_CVT_F32_UBYTE3_dpp8_gfx10
29896 { 13834, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13834 = V_CVT_FLR_I32_F32_dpp8_gfx10
29908 { 13846, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13846 = V_CVT_I16_F16_dpp8_gfx10
29918 { 13856, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13856 = V_CVT_I32_F32_dpp8_gfx10
29936 { 13874, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13874 = V_CVT_NORM_I16_F16_dpp8_gfx10
29946 { 13884, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13884 = V_CVT_NORM_U16_F16_dpp8_gfx10
29956 { 13894, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13894 = V_CVT_OFF_F32_I4_dpp8_gfx10
29999 { 13937, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13937 = V_CVT_RPI_I32_F32_dpp8_gfx10
30011 { 13949, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13949 = V_CVT_U16_F16_dpp8_gfx10
30021 { 13959, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #13959 = V_CVT_U32_F32_dpp8_gfx10
30089 { 14027, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14027 = V_EXP_F16_dpp8_gfx10
30099 { 14037, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14037 = V_EXP_F32_dpp8_gfx10
30118 { 14056, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14056 = V_FFBH_I32_dpp8_gfx10
30130 { 14068, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14068 = V_FFBH_U32_dpp8_gfx10
30142 { 14080, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14080 = V_FFBL_B32_dpp8_gfx10
30154 { 14092, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14092 = V_FLOOR_F16_dpp8_gfx10
30164 { 14102, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14102 = V_FLOOR_F32_dpp8_gfx10
30214 { 14152, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14152 = V_FRACT_F16_dpp8_gfx10
30224 { 14162, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14162 = V_FRACT_F32_dpp8_gfx10
30242 { 14180, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14180 = V_FREXP_EXP_I16_F16_dpp8_gfx10
30252 { 14190, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14190 = V_FREXP_EXP_I32_F32_dpp8_gfx10
30270 { 14208, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14208 = V_FREXP_MANT_F16_dpp8_gfx10
30280 { 14218, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14218 = V_FREXP_MANT_F32_dpp8_gfx10
30320 { 14258, 5, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14258 = V_INTERP_P2_F32_gfx10
30321 { 14259, 5, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14259 = V_INTERP_P2_F32_si
30322 { 14260, 5, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x2002ULL, ImplicitList4, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14260 = V_INTERP_P2_F32_vi
30346 { 14284, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14284 = V_LOG_F16_dpp8_gfx10
30356 { 14294, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14294 = V_LOG_F32_dpp8_gfx10
30709 { 14647, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14647 = V_MOV_B32_dpp8_gfx10
30721 { 14659, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14659 = V_MOV_FED_B32_dpp8_gfx10
30856 { 14794, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14794 = V_NOT_B32_dpp8_gfx10
30938 { 14876, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14876 = V_RCP_F16_dpp8_gfx10
30948 { 14886, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14886 = V_RCP_F32_dpp8_gfx10
30966 { 14904, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14904 = V_RCP_IFLAG_F32_dpp8_gfx10
30984 { 14922, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14922 = V_RNDNE_F16_dpp8_gfx10
30994 { 14932, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14932 = V_RNDNE_F32_dpp8_gfx10
31016 { 14954, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14954 = V_RSQ_F16_dpp8_gfx10
31026 { 14964, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14964 = V_RSQ_F32_dpp8_gfx10
31058 { 14996, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #14996 = V_SAT_PK_U8_I16_dpp8_gfx10
31072 { 15010, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #15010 = V_SIN_F16_dpp8_gfx10
31082 { 15020, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #15020 = V_SIN_F32_dpp8_gfx10
31094 { 15032, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #15032 = V_SQRT_F16_dpp8_gfx10
31104 { 15042, 5, 1, 8, 12, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #15042 = V_SQRT_F32_dpp8_gfx10
31269 { 15207, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #15207 = V_TRUNC_F16_dpp8_gfx10
31279 { 15217, 5, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #15217 = V_TRUNC_F32_dpp8_gfx10