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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc16240 { 178, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #178 = BUFFER_ATOMIC_ADD_ADDR64_RTN
16242 { 180, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #180 = BUFFER_ATOMIC_ADD_BOTHEN_RTN
16265 { 203, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #203 = BUFFER_ATOMIC_AND_ADDR64_RTN
16267 { 205, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #205 = BUFFER_ATOMIC_AND_BOTHEN_RTN
16305 { 243, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #243 = BUFFER_ATOMIC_DEC_ADDR64_RTN
16307 { 245, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #245 = BUFFER_ATOMIC_DEC_BOTHEN_RTN
16345 { 283, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #283 = BUFFER_ATOMIC_FMAX_ADDR64_RTN
16347 { 285, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #285 = BUFFER_ATOMIC_FMAX_BOTHEN_RTN
16365 { 303, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #303 = BUFFER_ATOMIC_FMIN_ADDR64_RTN
16367 { 305, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #305 = BUFFER_ATOMIC_FMIN_BOTHEN_RTN
16385 { 323, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #323 = BUFFER_ATOMIC_INC_ADDR64_RTN
16387 { 325, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #325 = BUFFER_ATOMIC_INC_BOTHEN_RTN
16405 { 343, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #343 = BUFFER_ATOMIC_OR_ADDR64_RTN
16407 { 345, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #345 = BUFFER_ATOMIC_OR_BOTHEN_RTN
16430 { 368, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #368 = BUFFER_ATOMIC_SMAX_ADDR64_RTN
16432 { 370, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #370 = BUFFER_ATOMIC_SMAX_BOTHEN_RTN
16450 { 388, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #388 = BUFFER_ATOMIC_SMIN_ADDR64_RTN
16452 { 390, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #390 = BUFFER_ATOMIC_SMIN_BOTHEN_RTN
16470 { 408, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #408 = BUFFER_ATOMIC_SUB_ADDR64_RTN
16472 { 410, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #410 = BUFFER_ATOMIC_SUB_BOTHEN_RTN
16490 { 428, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #428 = BUFFER_ATOMIC_SWAP_ADDR64_RTN
16492 { 430, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #430 = BUFFER_ATOMIC_SWAP_BOTHEN_RTN
16510 { 448, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #448 = BUFFER_ATOMIC_UMAX_ADDR64_RTN
16512 { 450, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #450 = BUFFER_ATOMIC_UMAX_BOTHEN_RTN
16530 { 468, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #468 = BUFFER_ATOMIC_UMIN_ADDR64_RTN
16532 { 470, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #470 = BUFFER_ATOMIC_UMIN_BOTHEN_RTN
16550 { 488, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #488 = BUFFER_ATOMIC_XOR_ADDR64_RTN
16552 { 490, 7, 1, 8, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, ImplicitList2, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #490 = BUFFER_ATOMIC_XOR_BOTHEN_RTN
20186 { 4124, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4124 = BUFFER_ATOMIC_ADD_ADDR64_RTN_gfx6_gfx7
20188 { 4126, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4126 = BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx10
20189 { 4127, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4127 = BUFFER_ATOMIC_ADD_BOTHEN_RTN_gfx6_gfx7
20190 { 4128, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4128 = BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi
20242 { 4180, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4180 = BUFFER_ATOMIC_AND_ADDR64_RTN_gfx6_gfx7
20244 { 4182, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4182 = BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx10
20245 { 4183, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4183 = BUFFER_ATOMIC_AND_BOTHEN_RTN_gfx6_gfx7
20246 { 4184, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4184 = BUFFER_ATOMIC_AND_BOTHEN_RTN_vi
20346 { 4284, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4284 = BUFFER_ATOMIC_DEC_ADDR64_RTN_gfx6_gfx7
20348 { 4286, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4286 = BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx10
20349 { 4287, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4287 = BUFFER_ATOMIC_DEC_BOTHEN_RTN_gfx6_gfx7
20350 { 4288, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4288 = BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi
20434 { 4372, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4372 = BUFFER_ATOMIC_FMAX_ADDR64_RTN_gfx6_gfx7
20436 { 4374, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4374 = BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx10
20437 { 4375, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4375 = BUFFER_ATOMIC_FMAX_BOTHEN_RTN_gfx6_gfx7
20470 { 4408, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4408 = BUFFER_ATOMIC_FMIN_ADDR64_RTN_gfx6_gfx7
20472 { 4410, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4410 = BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx10
20473 { 4411, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20081300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4411 = BUFFER_ATOMIC_FMIN_BOTHEN_RTN_gfx6_gfx7
20506 { 4444, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4444 = BUFFER_ATOMIC_INC_ADDR64_RTN_gfx6_gfx7
20508 { 4446, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4446 = BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx10
20509 { 4447, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4447 = BUFFER_ATOMIC_INC_BOTHEN_RTN_gfx6_gfx7
20510 { 4448, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4448 = BUFFER_ATOMIC_INC_BOTHEN_RTN_vi
20558 { 4496, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4496 = BUFFER_ATOMIC_OR_ADDR64_RTN_gfx6_gfx7
20560 { 4498, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4498 = BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx10
20561 { 4499, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4499 = BUFFER_ATOMIC_OR_BOTHEN_RTN_gfx6_gfx7
20562 { 4500, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4500 = BUFFER_ATOMIC_OR_BOTHEN_RTN_vi
20614 { 4552, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4552 = BUFFER_ATOMIC_SMAX_ADDR64_RTN_gfx6_gfx7
20616 { 4554, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4554 = BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx10
20617 { 4555, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4555 = BUFFER_ATOMIC_SMAX_BOTHEN_RTN_gfx6_gfx7
20618 { 4556, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4556 = BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi
20666 { 4604, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4604 = BUFFER_ATOMIC_SMIN_ADDR64_RTN_gfx6_gfx7
20668 { 4606, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4606 = BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx10
20669 { 4607, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4607 = BUFFER_ATOMIC_SMIN_BOTHEN_RTN_gfx6_gfx7
20670 { 4608, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4608 = BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi
20718 { 4656, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4656 = BUFFER_ATOMIC_SUB_ADDR64_RTN_gfx6_gfx7
20720 { 4658, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4658 = BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx10
20721 { 4659, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4659 = BUFFER_ATOMIC_SUB_BOTHEN_RTN_gfx6_gfx7
20722 { 4660, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4660 = BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi
20770 { 4708, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4708 = BUFFER_ATOMIC_SWAP_ADDR64_RTN_gfx6_gfx7
20772 { 4710, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4710 = BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx10
20773 { 4711, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4711 = BUFFER_ATOMIC_SWAP_BOTHEN_RTN_gfx6_gfx7
20774 { 4712, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4712 = BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi
20822 { 4760, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4760 = BUFFER_ATOMIC_UMAX_ADDR64_RTN_gfx6_gfx7
20824 { 4762, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4762 = BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx10
20825 { 4763, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4763 = BUFFER_ATOMIC_UMAX_BOTHEN_RTN_gfx6_gfx7
20826 { 4764, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4764 = BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi
20874 { 4812, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4812 = BUFFER_ATOMIC_UMIN_ADDR64_RTN_gfx6_gfx7
20876 { 4814, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4814 = BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx10
20877 { 4815, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4815 = BUFFER_ATOMIC_UMIN_BOTHEN_RTN_gfx6_gfx7
20878 { 4816, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4816 = BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi
20926 { 4864, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4864 = BUFFER_ATOMIC_XOR_ADDR64_RTN_gfx6_gfx7
20928 { 4866, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4866 = BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx10
20929 { 4867, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4867 = BUFFER_ATOMIC_XOR_BOTHEN_RTN_gfx6_gfx7
20930 { 4868, 7, 1, 8, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x81300010000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #4868 = BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi