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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19614 { 3552, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3552 = V_DOT2C_F32_F16_dpp
19617 { 3555, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3555 = V_DOT2C_I32_I16_dpp
19623 { 3561, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3561 = V_DOT4C_I32_I8_dpp
19628 { 3566, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3566 = V_DOT8C_I32_I4_dpp
19669 { 3607, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3607 = V_FMAC_F16_dpp
19673 { 3611, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3611 = V_FMAC_F32_dpp
19781 { 3719, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3719 = V_MAC_F16_dpp
19785 { 3723, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3723 = V_MAC_F32_dpp
30063 { 14001, 10, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #14001 = V_DOT2C_F32_F16_dpp_vi
30066 { 14004, 10, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #14004 = V_DOT2C_I32_I16_dpp_vi
30076 { 14014, 10, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #14014 = V_DOT4C_I32_I8_dpp_vi
30083 { 14021, 10, 1, 8, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #14021 = V_DOT8C_I32_I4_dpp_vi
30190 { 14128, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #14128 = V_FMAC_F32_dpp_vi
30425 { 14363, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #14363 = V_MAC_F16_dpp_vi
30431 { 14369, 10, 1, 8, 2, 0|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #14369 = V_MAC_F32_dpp_vi